Figure 1-1: Rocketio Multi-Gigabit Transceiver Block Diagram - Xilinx Virtex-4 RocketIO User Manual

Chapter 1: RocketIO Transceiver Overview
PACKAGE
PINS
AVCCAUXRX
1.2V
GNDA
TX/RX GND
AVCCAUXTX
1.2V
VCCINT
Fabric Power
Supply
Termination
VTRX
Supply RX
RXP
RXN
Termination
VTTX
Supply TX
TXP
TXN
FPGA FABRIC
(3)
RXCYCLELIMIT
(3)
TXCYCLELIMIT
RXCLKSTABLE
(3)
TXCALFAIL
TXCLKSTABLE
(3)
RXCALFAIL
RXCRCCLK
RXCRCDATAVALID
RXCRCDATAWIDTH[2:0]
RXCRCIN[63:0]
RXCRCINIT
RXCRCINTCLK
RXCRCOUT[31:0]
RXCRCPD
RXCRCRESET
TXCRCCLK
TXCRCDATAVALID
TXCRCDATAWIDTH[2:0]
TXCRCIN[63:0]
TXCRCINIT
TXCRCINTCLK
TXCRCOUT[31:0]
TXCRCPD
TXCRCRESET

Figure 1-1: RocketIO Multi-Gigabit Transceiver Block Diagram

36
MULTI-GIGABIT TRANSCEIVER CORE
Comma
Detect
Deserializer
Realign
64B/66B
Block Sync
Clock
Manager
Gearbox
(1)
Scrambler
Serializer
PLL
Calibration
Block
CRC
Block
Notes: (1) 64B/66B encoding/decoding is not supported.
(2) TXPCSHCLKOUT and RXPCSHCLKOUT ports are not supported.
(3) RXCALFAIL, RXCYCLELIMIT, TXCALFAIL, and TXCYCLELIMIT ports are not supported.
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64B/66B
64B/66B
(1)
Decoder
(1)
Descrambler
RX
Ring
Buffer
8B/10B
Decoder
Channel Bonding
and
(1)
Clock Correction
64B/66B
(1)
Encoder
TX
Ring
8B/10B
Buffer
Encoder
Clock/
Reset
Dynamic
Reconfiguration
Port
Fabric
Interface
Power Down
Virtex-4 RocketIO MGT User Guide
FPGA FABRIC
RXRECCLK1
RXLOCK
RXRECCLK2
RXPOLARITY RXPCSHCLKOUT
RXREALIGN
RXCOMMADET
ENPCOMMAALIGN
ENMCOMMAALIGN
RXCOMMADETUSE
RXSLIDE
(1)
RXDECC64B66BUSE
RXDEC8B10BUSE
RXDATA[63:0]
RXNOTINTABLE[7:0]
RXDISPERR[7:0]
RXCHARISK[7:0]
RXCHARISCOMMA[7:0]
RXRUNDISP[7:0]
RXSTATUS[5:0]
RXBUFERR
ENCHANSYNC
CHBONDI[4:0]
CHBONDO[4:0]
(1)
RXLOSSOFSYNC[1:0]
(1)
RXBLOCKSYNC64B66BUSE
(1)
RXDESCRAM64B66BUSE
(1)
RXIGNOREBTF
TXBUFERR
TXDATA[63:0]
TXBYPASS8B10B[7:0]
TXCHARISK[7:0]
TXCHARDISPMODE[7:0]
TXCHARDISPVAL[7:0]
TXKERR[7:0]
TXRUNDISP[7:0]
(1)
TXENC64B66BUSE
TXENC8B10BUSE
(1)
TXGEARBOX64B66BUSE
(1)
TXSCRAM64B66BUSE
TXLOCK
TXPOLARITY
TXINHIBIT
TXRESET
RXRESET
REFCLK1
REFCLK2
GREFCLK
RXUSRCLK
RXUSRCLK2
TXUSRCLK
TXUSRCLK2
TXPMARESET
RXPMARESET
TXOUTCLK1/TXPCSHCLKOUT
TXOUTCLK2
DADDR[7:0]
DI[15:0]
DCLK
DEN
DWE
DRDY
DO[15:0]
LOOPBACK[1:0]
RXDATAWIDTH[1:0]
RXINTDATAWIDTH[1:0]
TXDATAWIDTH[1:0]
TXINTDATAWIDTH[1:0]
POWERDOWN
ug076_apA_01_071707
UG076 (v4.1) November 2, 2008
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(2)
(2)