Xilinx Virtex-4 RocketIO User Manual page 311

R
Table C-19: Dynamic Reconfiguration Port Memory Map: MGTB Address 54–58
Bit
54 Def
15 0
14 0
13 0
12 0
11 0
10 0
9 0
8 0
RXEQ RESERVED
[47:32]
7 0
6 0
5 0
4 0
3 0
2 0
1 0
0 0
Notes:
1. The default X depends on the operation. See
2. This attribute should never be changed from the default setting. Otherwise the MGT can operate below optimum levels, compromising overall performance.
3. TXSLEWRATE is set to 0 by default. It must be set to 1 for all serial rates below 6.25 Gb/s. The RocketIO Wizard sets this attribute to 1.
Virtex-4 RocketIO MGT User Guide
UG076 (v4.1) November 2, 2008
55 Def
0
TXPRE_TAP_DAC
0
0
0 RESERVED
0 TXHIGHSIGNALEN
0 RESERVED
0
0
TXTERMTRIM
[15:0]
0
0
0 TXASYNCDIVIDE[1]
0 TXSLEWRATE
0
TXPOST_PRDRV_DAC
0
0
0 TXDAT_PRDRV_DAC[2]
Table C-28, page 320 for details.
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Address
(1)
56 Def
0
0
[2:0]
0
0
(2)
1
1
1
1
RESERVED
[3:0] [15:0]
0
0
X
(3)
0
1
1
(2)
[2:0]
1
(2)
1
Memory Map
57 Def 58
TXCRCINITVAL
N/A
[31:16]
Def
N/A
311