Ds1 Signals; E1 Signals; Sonet/Sdh Signals - Alcatel-Lucent 7450 Basic System Configuration Manual

Network Synchronization
SSM allows equipment to autonomously provision and reconfigure (by reference switching)
their synchronization references, while helping to avoid the creation of timing loops. These
messages are particularly useful to allow synchronization reconfigurations when timing is
distributed in both directions around a ring.
The following sections provide details about the SSM message functionality for different
signal types. These functions apply to all platforms that support the given signal type.

DS1 Signals

DS1 signals can carry an indication of the quality level of the source generating the timing
information using the SSM transported within the 1544 Kbit/s signal's Extended Super Frame
(ESF) Data Link (DL) as specified in Recommendation G.704. No such provision is extended
to SF formatted DS1 signals.
The format of the data link messages in ESF frame format is "0xxx xxx0 1111 1111",
transmitted rightmost bit first. The six bits denoted "xxx xxx" contain the actual message;
some of these messages are reserved for synchronization messaging. It takes 32 frames (such
as 4 ms) to transmit all 16 bits of a complete DL.

E1 Signals

E1 signals can carry an indication of the quality level of the source generating the timing
information using the SSM as specified in Recommendation G.704.
One of the Sa4 to Sa8 bits, (the actual Sa bit is for operator selection), is allocated for
Synchronization Status Messages. To prevent ambiguities in pattern recognition, it is
necessary to align the first bit (San1) with frame 1 of a G.704 E1 multi-frame.
The numbering of the San (n = 4, 5, 6, 7, 8) bits. A San bit is organized as a 4-bit nibble San1
to San4. San1 is the most significant bit; San4 is the least significant bit.
The message set in San1 to San4 is a copy of the set defined in SDH bits 5 to 8 of byte S1.

SONET/SDH Signals

The SSM of SDH and SONET interfaces is carried in the S1 byte of the frame overhead. Each
frame contains the four bit value of the QL.
256 Basic System Configuration Guide