Alcatel-Lucent 7450 Basic System Configuration Manual page 254

Network Synchronization
The BITS ports accept T1 or E1 signal formats. Some hardware also supports the 2048 kHz
signal format. The format must be common between all BITSin and BITSout ports.
All settings of the signal characteristics for the BITS input apply to both ports. When the
active CPM considers the BITS input as a possible reference, it will consider first the BITS
input port on the active CPM or CCM followed by the BITS input port on the standby CPM
or CCM in that relative priority order. This relative priority order is in addition to the user-
definable ref-order. For example, a ref-order of bits ref1 ref2 would actually be BITS in
(active CPM or CCM), followed by BITS in (standby CPM or CPM), followed by ref1,
followed by ref2. When ql-selection is enabled, the QL of each BITS input port is viewed
independently. The higher QL source is chosen.
The 7750 SR-c4 platform has a CFM, there are two BITS input ports and two BITS output
ports on this one module. These two ports are provided for BITS redundancy for the chassis.
All settings of the signal characteristics for the BITS input applies to both ports. This includes
the ql-override setting. When the CFM considers the BITS input as a possible reference, it
will consider first the BITS input port "bits1" followed the BITS input port "bits2" in that
relative priority order. This relative priority order is in addition to the user definable ref-
order. For example, a ref-order of bits ref1 ref2 would actually be "bits1", followed by
"bits2", followed by ref1, followed by ref2. When ql-selection is enabled, the QL of each
BITS input port is viewed independently. The higher QL source is chosen.
The BITS output ports can be configured to provided either the unfiltered recovered line
clock from a line card port or the output of the central clock. The first case would be used if
the port was connected to deliver an input reference directly to dedicated timing device in the
facility (BITS or SASE device). The second case would be used to test the quality of the
clocking used by the router.
When QL selection mode is disabled, then the reversion setting controls when the central
clock can re-select a previously failed reference.
The
revertive modes:
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• T1/E1 CES channel (adaptive clocking) (7750 SR only)
• Synchronous Ethernet ports
• T1/E1 port (7750 SR only)
• BITS port on a Channelized OC3/STM1 CES CMA (7750 SR-c12 only)
• BITS port on the CPM, CFM, or CCM module
• 10GE ports in WAN PHY mode
• IEEE 1588v2 slave port (PTP) (7450 ESS and 7750 SR only)
Table 30 shows the selection followed for two reference in both revertive and non-
Basic System Configuration Guide