Spi 2 Programming Model; Spi 2 Data Register; Spi 2 Data Register Timing; Table 13-7 Spi 2 Data Register Description - Motorola MC68VZ328 User Manual

SPI 2 Programming Model

13.6 SPI 2 Programming Model
This section provides information for programming SPI 2.
13.6.1

SPI 2 Data Register

The SPI 2 data (SPIDATA2) register exchanges data with external slave devices. The bit position
assignments for this register are shown in the following register display. The settings for this register are
described in Table 13-7.
SPIDATA2
BIT
14
15
TYPE rw rw
0 0
RESET
Name
DATA Data—Top of SPI 2's RxFIFO (8 × 16)
Bits 15–0
13.6.2

SPI 2 Data Register Timing

The data bits are exchanged with the external device. The data must be loaded before the XCH bit in the
SPICONT2 register is set. In phase 0, data is presented on the SPITXD pin when this register is written. In
phase 1, the first data bit is presented on the first SPICLK2 edge. At the end of the exchange, data from the
peripheral is present in this register and bit 0 is the least significant bit. As data is shifted MSB first,
outgoing data is automatically MSB justified. For example, if the exchange length is 10 bits, the first bit
presented to the external device will be bit 9, followed by the remaining bits.
Writes to this field are ignored while the ENABLE bit is clear or while the
XCH bit is set. This field contains unknown data if it is read while the XCH
bit is set.
13-14
SPI 2 Data Register
13 12 11 10
rw rw rw rw
0 0 0 0
Table 13-7. SPI 2 Data Register Description
Description
MC68VZ328 User's Manual
9 8 7 6
DATA
rw rw rw rw
0 0 0 0
0x0000
The data in this register has no meaning if the RR
bit in the interrupt control/status register is clear.
NOTE:
0x(FF)FFF800
5 4 3 2 1
rw rw rw rw rw
0 0 0 0 0
Setting
BIT
0
rw
0