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PDIRQEG
BIT 7
TYPE
RESET
Table 10-25. Port D Interrupt Request Edge Register Description
Name
Reserved
Reserved
Bits 7–4
IQEGx
Edge Enable—The polarity of the rising or
Bits 3–0
falling edge is selected by the POLx bits.
10.4.6
Port E Registers
Port E is composed of the following 8-bit general-purpose I/O registers:
•
Port E direction register (PEDIR)
•
Port E data register (PEDATA)
•
Port E pull-up enable register (PEPUEN)
•
Port E select register (PESEL)
Each signal in the PEDATA register connects to an external pin. As with the other ports, each bit on Port E
is individually configured. Port E is multiplexed with the serial peripheral interface (SPI) and UART
signals.
10.4.6.1
Port E Direction Register
The Port E direction register controls the direction (input or output) of the line associated with the
PEDATA bit position. When the data bit is assigned to a dedicated I/O function by the PESEL register, the
DIR bits are ignored. The settings for the bit positions of the PEDIR register are shown in Table 10-26.
PEDIR
BIT 7
DIR7
TYPE
rw
0
RESET
Name
DIRx
Direction—These bits control the direction of the pins in an 8-bit
Bits 7–0
system. They reset to 0.
Port D Interrupt Request Edge Register
6
5
0
0
0
Description
Port E Direction Register
6
5
DIR6
DIR5
rw
rw
0
0
Table 10-26. Port E Direction Register Description
Description
I/O Ports
4
3
IQEG3
IQEG2
rw
rw
0
0
0x00
Setting
These bits are reserved and should be set to 0.
0 = Level-sensitive interrupts are selected.
1 = INT[3:0] edge-sensitive interrupts are selected.
4
3
2
DIR4
DIR3
DIR2
rw
rw
rw
0
0
0
0x00
0 = Input
1 = Output
Programming Model
0x(FF)FFF41F
2
1
BIT 0
IQEG1
IQEG0
rw
rw
0
0
0
0x(FF)FFF420
1
BIT 0
DIR1
DIR0
rw
rw
0
0
Setting
10-21
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