Modules Of The Mc68Vz328; Memory Controller; Clock Generation Module And Power Control Module - Motorola MC68VZ328 User Manual

Modules of the MC68VZ328

Mnemonic
EORI Exclusive OR immediate
EORI to CCR Exclusive OR immediate to condition codes
EORI to SR Exclusive OR immediate to status register
EXG Exchange registers
EXT Sign extend
JMP Jump
JSR Jump to subroutine
LEA Load effective address
LINK Link stack
LSL Logical shift left
LSR Logical shift right
MOVE Move
MOVEA Move address
1.3 Modules of the MC68VZ328
In addition to the powerful 68000 processor, the DragonBall VZ contains a wide variety of peripheral
interface and control modules. The following subsections provide brief descriptions of these modules and
how they operate.
1.3.1

Memory Controller

The memory controller provides a glueless interface to most memory chips on the market. It supports flash,
ROM, SRAM, different DRAM types (EDO RAM and Fast Page Mode), and synchronous DRAM. Either
one or two banks of DRAM may be used, and each bank can be a maximum of 32 Mbyte. For a more
complete explanation of how memory is configured and controlled, see Chapter 3, "Memory Map."
1.3.2

Clock Generation Module and Power Control Module

The module containing the clock synthesizer operates with either an external crystal or an external
oscillator to provide a stable clock source for the internal clock generation module (CGM). The output
frequency can be adjusted by writing to the CGM frequency select register. The CGM can be disabled to
shut down the system clock divider chain for maximum power saving, while the real-time clock (RTC) and
DRAM controller remain active. The power control module can be configured to control the CPU cycles to
optimize power consumption. The power control module offers three power-saving modes: normal, doze,
1-8
Table 1-2. Instruction Set (Continued)
Description
MC68VZ328 User's Manual
Mnemonic
STOP Stop
SUB Subtract
SUBA Subtract address
SUBI Subtract immediate
SUBQ Subtract quick
SUBX Subtract with extend
SWAP Swap data register halves
TAS Test and set operand
TRAP Trap
TRAPV Trap on overflow
TST Test
UNLK Unlink
Description