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10.4.1.1
Port A Direction Register
The Port A direction register controls the direction (input or output) of the line associated with the
PADATA bit position. The settings for the bit positions are shown in Table 10-4.
PADIR
BIT 7
DIR7
TYPE
rw
0
RESET
Name
DIRx
Direction—These bits control the direction of the pins in an 8-bit
Bits 7–0
system.
10.4.1.2
Port A Data Register
The eight PADATA bits control or report the data on the pins while the associated SELx bits are high.
While the DIRx bits are high (output), the Dx bits control the pins. While the DIRx bits are low (input), the
Dx bits report the signal driving the pins. The Dx bits can be written at any time. Bits that are configured as
inputs will accept the data, but the data written to each cannot be accessed until the respective pin is
configured as an output. The actual value on the pin is reported when these bits are read, regardless of
whether they are configured as input or output. The settings for the bit positions are shown in Table 10-5.
PADATA
BIT 7
TYPE
RESET
Name
Description
Dx
Data—These bits reflect the
Bits 7–0
status of the I/O signal in an
8-bit system.
Port A Direction Register
6
5
DIR6
DIR5
rw
rw
0
0
Table 10-4. Port A Direction Register Description
Description
Port A Data Register
6
5
D7
D6
D5
rw
rw
rw
1
1
1
*Actual bit value depends on external circuits connected to pin.
Table 10-5. Port A Data Register Description
0 = Drives the output signal low when DIRx is set to 1 or the
1 = Drives the output signal high when DIRx is set to 1 or the
I/O Ports
4
3
DIR4
DIR3
rw
rw
0
0
0x00
4
3
D4
D3
rw
rw
1
1
0xFF*
Setting
external signal is low when DIRx is set to 0
external signal is high when DIRx is set to 0
Programming Model
0x(FF)FFF400
2
1
BIT 0
DIR2
DIR1
DIR0
rw
rw
rw
0
0
0
Setting
0 = Input
1 = Output
0x(FF)FFF401
2
1
BIT 0
D2
D1
D0
rw
rw
rw
1
1
1
10-7
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