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PWM 2
15.5
PWM 2
PWM 2 is a 16-bit PWM module that is compatible with the one used in the original DragonBall processor,
MC68328. Besides the difference in the PWM code size (8-bit versus 16-bit), the major difference between
PWM 2 and PWM 1 is that PWM 2 does not have a data FIFO. Figure 15-4 illustrates the block diagram of
the pulse-width modulator unit 2.
SYSCLK
15.5.1
PWM 2 Control Register
This register controls how the overall pulse-width modulator operates. Output pin status is also maintained
in this register. The register bit assignments are shown in the following register display. The register
settings are described in Table 15-5.
PWMC2
BIT 15
14
PWMIRQ
IRQEN
TYPE
rw
rw
0
0
RESET
Name
PWMIRQ
PWM Interrupt—This bit indicates that a period compare posted
Bit 15
an interrupt. This bit may also be set to immediately post a PWM
interrupt for debugging purposes. This bit is cleared after it is
read while set. If the IRQEN bit is 0, this bit can be polled for the
period comparator status.
IRQEN
Interrupt Enable—This bit enables the PWM interrupt.
Bit 14
Reserved
Reserved
Bits 13–9
LOAD
Load New Setting—This bit forces a new period value and width
Bit 8
data to the registers. It automatically clears itself after the loading
operation has been performed.
15-8
Width Compare
Prescaler
Period Compare
Figure 15-4. PWM 2 Block Diagram
PWM 2 Control Register
13
12
11
10
9
0
0
0
0
0
Table 15-5. PWM 2 Control Register Description
Description
MC68VZ328 User's Manual
Output
Control
Counter
8
7
6
5
LOAD
PIN
POL
rw
rw
rw
0
0
0
0
0x0000
PWMO
0x(FF)FFF510
4
3
2
1
PWMEN
CLKSEL
rw
rw
rw
0
0
0
0
Setting
0 = No PWM period rollover.
1 = PWM period rolled over.
0 = Disable PWM interrupt.
1 = Enable PWM interrupt.
These bits are reserved and
should be set to 0.
See description.
BIT
0
rw
0
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