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PBDIR
BIT 7
DIR7
TYPE
rw
0
RESET
Name
DIRx
Direction—These bits control the direction of the pins. They reset
Bits 7–0
to 0. With the exception of bit 6, if a bit is selected as a dedicated
I/O in PBSEL, the DIR bit is ignored
10.4.2.2
Port B Data Register
The settings for the PBDATA bit positions are shown in Table 10-8.
PBDATA
BIT 7
TYPE
RESET
Name
Dx
Data—These bits reflect the
Bits 7–0
status of the I/O signal in an
8-bit system.
Port B is multiplexed with chip-select, DRAM control, TIN/TOUT, and PWM dedicated I/O signals.
These pins can be programmed as GPIO when these other assignments are not used.
These bits control or report the data on the pins while the associated SELx bits are high. While the DIRx
bits are high (output), the Dx bits control the pins. While the DIRx bits are low (input), the Dx bits report
the signal driving the pins. The Dx bits can be written at any time. Bits that are configured as inputs will
accept the data, but the data written to each cannot be accessed until the corresponding pin is configured as
an output. The actual value on the pin is reported when these bits are read, regardless of whether they are
configured as input or output.
Port B Direction Register
6
5
DIR6
DIR5
rw
rw
0
0
Table 10-7. Port B Direction Register Description
Description
Port B Data Register
6
5
D7
D6
D5
rw
rw
rw
1
1
1
*Actual bit value depends on external circuits connected to pin.
Table 10-8. Port B Data Register Description
Description
4
3
DIR4
DIR3
rw
rw
0
0
0x00
.
4
3
D4
D3
rw
rw
1
1
0xFF*
0 = Drives the output signal low when DIRx is set to 1 or the
external signal is low when DIRx is set to 0
1 = Drives the output signal high when DIRx is set to 1 or the
external signal is high when DIRx is set to 0
I/O Ports
Programming Model
0x(FF)FFF408
2
1
DIR2
DIR1
rw
rw
0
0
Setting
0 = Inputs
1 = Output
0x(FF)FFF409
2
1
D2
D1
rw
rw
1
1
Setting
BIT 0
DIR0
rw
0
BIT 0
D0
rw
1
10-9
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