Peripheral Control Register; Table 5-2 Peripheral Control Register Description - Motorola MC68VZ328 User Manual

Programming Model
5.2.2

Peripheral Control Register

This register controls the PWM logical block operation, timer TIN/TOUT signal, and UART UCLK
signal. The bit assignments for the register are shown in the following register display. The settings for the
bits in the register are listed in Table 5-2.
PCR
BIT 7
TYPE
0
RESET
Name
Reserved Reserved
Bits 7–5
UCLK UART Clock Pin Configuration—When UCLK
Bit 4 of UART 1 and UART 2 is configured to output
signal, this bit selects UART 1's or UART 2's
UCLK for UCLK pin output. When UCLK of
UART 1 and UART 2 is configured as input, this
bit is "don't care," and UCLK pin is an input signal.
P[1:0] PWM Outputs Logic Operation—These bits
Bits 3–2 select the logical combination for final PWM pin
output.
T[1:0] TIN/TOUT Signal Configuration—These 2 bits
Bits 1–0 are used to configure the external TIN/TOUT sig-
nal when pin PB6/TIN/TOUT is selected as
TIN/TOUT function. For detailed information on
using this function, see Section 12.1.4,
"TOUT/TIN/PB6 Pin," on page 12-3.
5-4
Peripheral Control Register
6 5
0 0
Table 5-2. Peripheral Control Register Description
Description
MC68VZ328 User's Manual
4 3
UCLK P[1:0]
rw rw
0 0
0x00
Do not use these bits.
0 = UCLK pin is connected to UART 1.
1 = UCLK pin is connected to UART 2.
00 = 8-bit PWM out only (default).
01 = 16-bit PWM out only.
10 = Logic OR of both PWM outputs.
11 = Logic AND of both PWM outputs.
00 = TIN/TOUT is connected to Timer 1.
01 = TIN/TOUT is connected to Timer 2.
10 = Timer 2 OUT -> Timer 1 IN; TIN -> Timer 2
(DIR6 = 0), or TOUT -> Timer 1 (DIR6 = 1).
11 = Timer 1 OUT -> Timer 2 IN; TIN -> Timer 1
(DIR6 = 0), or TOUT -> Timer 2 (DIR6 = 1).
0x(FF)FFF003
2 1 BIT 0
T[1:0]
rw rw rw
0 0 0
Setting