Sdram Power-Down Register; Table 7-10 Sdram Power-Down Register Description - Motorola MC68VZ328 User Manual

Programming Model
7.3.4

SDRAM Power-down Register

This register controls how the SDRAM and the MC68VZ328 operate during a power-down operation. The
bit position and values are shown in the following register display. The details about the register settings
are described in Table 7-10.
SDPWDN
BIT
14
15
APEN PDEN
TYPE rw rw
0 0
RESET
Table 7-10. SDRAM Power-down Register Description
Name
APEN SDRAM Active Power-down Enable—The bit is set to
Bit 15 make the SDRAM Chip Enable signal go low immediately
when the DRAM controller is not sending a command, writ-
ing data, or reading data with the SDRAM.
PDEN SDRAM Precharged Power-down Enable—The bit is set
Bit 14 to make the SDRAM Chip Enable signal go low when the
DRAM controller is not sending a command after the
SDRAM is precharged for a certain time. The time depends
on the value in PDTOUT[3:0].
Reserved Reserved
Bits 13–12
PDTOUT [3:0] SDRAM Precharged Power-down Time Out—The bit is
Bits 11–8 set to make the SDRAM Chip Enable signal go low when a
time out occurs when the PDEN bit is set. Each binary unit
represents a maximum of 128 clocks. When in power-down
mode, SDRAM can be woken by a CPU or LCD access.
Reserved Reserved
Bits 7–0
7-18
SDRAM Power-down Register
13 12 11 10
PDTOUT[3:0]
rw rw
0 0 0 0
Description
MC68VZ328 User's Manual
9 8 7 6 5
rw rw
0 0 0 0 0
0x0000
0 = APEN disabled.
1 = APEN enabled.
0 = PDEN disabled.
1 = PDEN enabled.
These bits are reserved and
should be set to 0.
See the description.
These bits are reserved and
should be set to 0.
0x(FF)FFFC06
BIT
4 3 2 1
0
0 0 0 0 0
Settings