Page-Hit Lcd Dma Cycle For Sdram (Cas Latency = 1); Figure 19-26 Page-Hit Lcd Dma Cycle For Sdram Timing Diagram - Motorola MC68VZ328 User Manual

AC Electrical Characteristics
19.3.25 Page-Hit LCD DMA Cycle for SDRAM (CAS
Latency = 1)
Figure 19-26 shows the timing diagram for the page-hit LCD DMA cycle for SDRAM. The signal values
and units of measure for this figure are found in Table 19-16 on page 19-31. Detailed information about
the operation of individual signals can be found in both Chapter 8, "LCD Controller," and Chapter 7,
"DRAM Controller."
SDCLK
SCKEN
A[16:1]/MD[15:0]
SDA10
CS
RAS
CAS
D[15:0]
WE
DQM
DTACK
Figure 19-26. Page-Hit LCD DMA Cycle for SDRAM Timing Diagram
19-30
Col n Col n+1
Data n
Read
Command
Read
Command
MC68VZ328 User's Manual
Col n+2 Col n+3
Data n+1 Data n+2 Data n+3
Read
Command
Read
Command