Table 16-1 Ice Module Address Compare And Mask Registers Description - Motorola MC68VZ328 User Manual

ICEMACR
BIT
30
31
AC3 AC AC2
1 30
TYPE rw rw
0 0
RESET
BIT
14
15
AC1 AC AC1
5 14
TYPE rw rw
0 0
RESET
ICEMAMR
BIT
30
31
AM3 AM AM2
1 30
TYPE rw rw
0 0
RESET
BIT
14
15
AM1 AM AM1
5 14
TYPE rw rw
0 0
RESET
Table 16-1. ICE Module Address Compare and Mask Registers Description
Name
ACx Address Compare 31–0—These bits represent the value of the
Bits 31–0 execution/bus breakpoint address. A match of address bits 31–0
with qualification of AS will generate a match signal.
AMx Address Mask 31–0—These bits mask the corresponding bits in
Bits 31–0 the ACx field. With this masking scheme, a break can be made
when the core is accessing a certain range of addresses.
ICE Module Address Compare Register
29 28 27 26
AC2 AC2 AC2
9 8 7 6
rw rw rw rw
0 0 0 0
13 12 11 10
AC1 AC1 AC1
3 2 1 0
rw rw rw rw
0 0 0 0
ICE Module Address Mask Register
29 28 27 26
AM2 AM2 AM2
9 8 7 6
rw rw rw rw
0 0 0 0
13 12 11 10
AM1 AM1 AM1
3 2 1 0
rw rw rw rw
0 0 0 0
Description
In-Circuit Emulation
25 24 23 22 21
AC AC AC AC AC
25 24 23 22 21
rw rw rw rw rw
0 0 0 0 0
0x0
9 8 7 6 5
AC AC AC AC AC
9 8 7 6 5
rw rw rw rw rw
0 0 0 0 0
0x0
25 24 23 22 21
A A A A A
M2 M2 M2 M2 M2
5 4 3 2 1
rw rw rw rw rw
0 0 0 0 0
0x0000
9 8 7 6 5
A A A A A
M9 M8 M7 M6 M5
rw rw rw rw rw
0 0 0 0 0
0x0000
Programming Model
0x(FF)FFFFFD00
BIT
20 19 18 17
16
AC AC AC AC
AC16
20 19 18 17
rw rw rw rw rw
0 0 0 0 0
4 3 2 1 BIT 0
AC AC AC AC
AC0
4 3 2 1
rw rw rw rw rw
0 0 0 0 0
0x(FF)FFFFFD04
BIT
20 19 18 17
16
A A A A
AM1
M2 M1 M1 M1
6
0 9 8 7
rw rw rw rw rw
0 0 0 0 0
4 3 2 1 BIT 0
A A A A
AM0
M4 M3 M2 M1
rw rw rw rw rw
0 0 0 0 0
Setting
See description.
0 = The address is compared
to the current address
cycle.
1 = Forces a true comparison
("don't care") on the
corresponding bit.
16-5