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Chapter 7
DRAM Controller
This chapter describes the DRAM controller for the MC68VZ328. The operation of the DRAM controller
is closely linked to the chip-select logic. Please refer to Chapter 6, "Chip-Select Logic," for more details.
7.1
Introduction to the DRAM Controller
The DRAM controller provides a glueless interface for either 8-bit or 16-bit DRAM. It supports EDO
RAM, Fast Page Mode, and synchronous DRAM. The DRAM controller provides Row Address Strobe
(RAS) and Column Address Strobe (CAS) signals for up to a maximum of two banks of DRAM. In
addition to controlling DRAM, the DRAM controller provides support for LCD controller burst accesses.
The DRAM controller has the following features:
•
68000 CPU zero wait-state operation support
•
CAS-before-RAS refresh cycles and self-refresh mode DRAM support
•
8- and 16-bit port DRAM support
•
Fast Page Mode and EDO RAM modes or synchronous burst for LCD DMA access cycles
•
Programmable refresh rate
•
Support for a maximum of two banks of DRAM
•
Programmable row and column address size with symmetrical or asymmetrical addressing
•
Support for up to 16 Mbyte
A block diagram of the DRAM controller appears in Figure 7-1 on page 7-2.
×
×
16 or 32 Mbyte
8 DRAM or SDRAM
DRAM Controller
7-1
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