Page-Miss Sdram Cpu Write Cycle (Cas Latency = 1); Figure 19-18 Page-Miss Sdram Cpu Write Cycle Timing Diagram - Motorola MC68VZ328 User Manual

AC Electrical Characteristics
19.3.17 Page-Miss SDRAM CPU Write Cycle (CAS
Latency = 1)
Figure 19-18 shows the timing diagram for the page-miss SDRAM CPU write cycle for 8-bit SDRAM.
The signal values and units of measure for this figure are found in Table 19-16 on page 19-31. Detailed
information about the operation of individual signals can be found in both Chapter 8, "LCD Controller,"
and Chapter 7, "DRAM Controller."
S0
SDCLK
SCKEN
A[16:1]/MD[15:0]
SDA10
CS
RAS
CAS
D[15:0]
WE
DQM
DTACK
Figure 19-18. Page-Miss SDRAM CPU Write Cycle Timing Diagram
19-22
S1 S2 S3 S4 S4 S4
Bank
1=All Bank
8
11
Precharge
Command
MC68VZ328 User's Manual
S5 S6 S7
Row Col
17
15
Active
Command
Write
Command