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1
1
-------------- -
--------------------- -
T
=
l
60 Hz
240 lines
=
69.4 s
During the same period, the line buffer must be filled. The following T
cycle will hold up the bus:
320 pixels
T
=
---------------------------------------------------------------------------------------------------- -
DMA
=
Thus, the percentage of host bus time taken up by the LCD controller's DMA is P
4.8' s
P
=
-------------------- -
DMA
69.4' s
=
6.92'%
8.2.5
Self-Refresh Mode
The LCD driver from Epson was used as a reference for the design of the refresh mode. In self-refresh
mode, the LCD module will update the screen periodically from internal RAM using the LP and FRM
pulse.
8.2.5.1
Entering Self-Refresh Mode
Setting the self-refresh register bit 7 to 1 means that the LSCLK and LD will remain 0 when the end of the
frame is reached. The LP and FRM pulse continue as in normal mode, but there are no pulses on either the
LSCLK or LD.
8.2.5.2
Canceling Self-Refresh Mode
Setting the self-refresh register bit 7 to 0 means that the normal mode is entered when the end of the frame
is reached. On entering normal mode, data is sent out from the beginning of the page.
2 bits per pixel
16.67 MHz 16-bit bus
4.8 s
LCD Controller
LCD Controller Operation
duration is how long the DMA
DMA
2 clocks
:
DMA
8-9
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