Status Of I/O Ports During Reset; Warm Reset; Table 10-1 Dedicated I/O Functions Of Ports - Motorola MC68VZ328 User Manual

Status of I/O Ports During Reset

Port Dedicated I/O Module
A Lower byte of data bus
B Chip-select
C LCD controller
D Interrupt controller
E SPI
F DRAM controller
LCD contrast
G Bus control
J UART
K Bus control
M DRAM controller
10.2 Status of I/O Ports During Reset
Two types of resets affect the states of the MC68VZ328's I/O ports: warm reset and power-up reset. A
warm reset refers to any reset initiated while power to the processor remains uninterrupted. A power-up
reset occurs the first time power is supplied to the MC68VZ328. Power-up resets are also called cold start
resets.
10.2.1

Warm Reset

Figure 10-1 on page 10-3 details timing during a warm reset. All I/O ports, except Ports B and M, reset to
their default states on assertion of the reset signal and remain at their default states during the time period
labeled Reset Assertion Time Length. The port default state is determined by the register reset values of
the I/O port registers. Register reset values are found in Table 3-1 on page 3-2 and Table 3-2 on page 3-8.
Ports B and M maintain their previous programmed states on reset assertion and retain their states during
the Reset Assertion Time Length. The previous states of Ports B and M before reset assertion are, for the
purposes of the figure, assumed.
10-2
Table 10-1. Dedicated I/O Functions of Ports
Dedicated I/O Module
DRAM controller
DRAM controller
CGM
Chip-select
In-circuit emulation
SPI
LCD controller
MC68VZ328 User's Manual
Dedicated I/O Module
GP timers
UART
Address bits 23–20
Address bit 0
SPI
Dedicated I/O Module
PWM output
Bus control
Interrupt request 5