I/O Drive Control Register; Table 5-4 I/O Drive Control Register Description - Motorola MC68VZ328 User Manual

Programming Model
5.2.4

I/O Drive Control Register

This register controls the driving strength of all I/O signals. By default, all pins are defaulted to 4 mA
driving current. After reset, system software should select 2 mA driving for those signals that do not need
high-current driving for power saving. The bit assignments for the register are shown in the following
display. The settings for the bits in the register are listed in Table 5-4.
IODCR
BIT 15 14
TYPE
0 0
RESET
Name
Reserved Reserved
Bits 15–13
AB Address Bus Signals I/O Drive Control—It should be
Bit 12 noted that A[23:20] are controlled by the PF bit.
DB Upper Data Bus Signals I/O Drive Control—The
Bit 11 lower data bus is controlled by the PA bit.
CB Control Bus Signals—Only those signals or functions
Bit 10 not multiplexed with GPIO are controlled by this bit.
PM–PA Port M to Port A Group I/O Drive Control—Each bit
Bits 9–0 controls the drive current for the lines in the respective
port.
5-6
I/O Drive Control Register
13 12 11 10
AB DB CB
rw rw rw
0 1 1 1
Table 5-4. I/O Drive Control Register Description
Description
MC68VZ328 User's Manual
9 8 7 6 5
PM PK PJ PG PF
rw rw rw rw rw
1 1 1 1 1
0x1FFF
Do not use these bits.
0 = I/O drive current for each pin is 2 mA.
1 = I/O drive current for each pin is 4 mA.
0 = I/O drive current for each pin is 2 mA.
1 = I/O drive current for each pin is 4 mA.
0 = I/O drive current for each pin is 2 mA.
1 = I/O drive current for each pin is 4 mA.
0 = I/O drive current for each pin is 2 mA.
1 = I/O drive current for each pin is 4 mA.
0x(FF)FFF008
4 3 2 1 BIT 0
PE PD PC PB PA
rw rw rw rw rw
1 1 1 1 1
Setting