Port J Data Register; Port J Dedicated I/O Functions; Table 10-42 Port J Data Register Description; Table 10-43 Port J Dedicated I/O Function Assignments - Motorola MC68VZ328 User Manual

Programming Model
10.4.9.2

Port J Data Register

The bit settings for the PJDATA register are shown in Table 10-42.
PJDATA
BIT 7
TYPE
RESET
Name Description
Dx Data—These bits reflect the
Bits 7–0 status of the I/O signal in an
8-bit system.
Port J is multiplexed with the configurable SPI (with internal FIFO) and UART 2 signals. These pins can
be programmed as GPIO when the dedicated I/O signals are not in use.
These bits control or report the data on the pins while the associated SELx bits are high. While the DIRx
bits are high (output), the Dx bits control the pins. While the DIRx bits are low (input), the Dx bits report
the signal driving the pins. The Dx bits can be written at any time. Bits that are configured as inputs will
accept the data, but the data written to each cannot be accessed until the corresponding pin is configured as
an output. The actual value on the pin is reported when these bits are read, regardless of whether they are
configured as input or output.
10.4.9.3

Port J Dedicated I/O Functions

The eight PJDATA lines are multiplexed with the dedicated I/O signals whose assignments are shown in
Table 10-43.
Table 10-43. Port J Dedicated I/O Function Assignments
Bit
0
1
2
3
4
5
6
10-32
Port J Data Register
6 5
D7 D6 D5
rw rw rw
1 1 1
*Actual bit value depends on external circuits connected to pin.
Table 10-42. Port J Data Register Description
0 = Drives the output signal low when DIRx is set to 1 or the
1 = Drives the output signal high when DIRx is set to 1 or the
GPIO Function
MC68VZ328 User's Manual
4 3
D4 D3
rw rw
1 1
0xFF*
Setting
external signal is low when DIRx is set to 0
external signal is high when DIRx is set to 0
Dedicated I/O Function
Data bit 0
Data bit 1
Data bit 2
Data bit 3
Data bit 4
Data bit 5
Data bit 6
0x(FF)FFF439
2 1 BIT 0
D2 D1 D0
rw rw rw
1 1 1
MOSI
MISO
SPICLK1
SS
RXD2
TXD2
RTS2