Page 1 MCF5272 ColdFire ® Integrated Microprocessor User’s Manual MCF5272UM/D Rev. 0, 02/2001...
Page 2 Motorola product could create a situation where personal injury or death may occur. Should Buyer purchase or...
Page 3 Overview ColdFire Core Hardware Multiply/Accumulate (MAC) Unit Local Memory Debug Support System Integration Module (SIM) Interrupt Controller Chip-Select Module SDRAM Controller DMA Controller Module Ethernet Module Universal Serial Bus (USB) Physical Layer Interface Controller (PLIC) Queued Serial Peripheral Interface (QSPI) Module Timer Module UART Modules General-Purpose I/O Module...
Page 4 Overview ColdFire Core Hardware Multiply/Accumulate (MAC) Unit Local Memory Debug Support System Integration Module (SIM) Interrupt Controller Chip-Select Module SDRAM Controller DMA Controller Module Ethernet Module Universal Serial Bus (USB) Physical Layer Interface Controller (PLIC) Queued Serial Peripheral Interface (QSPI) Module Timer Module UART Modules General-Purpose I/O Module...
Page 5: Table Of Contents
CONTENTS Paragraph Page Title Number Number About This Book Chapter 1 Overview MCF5272 Key Features..................1-1 MCF5272 Architecture ..................1-4 1.2.1 Version 2 ColdFire Core................. 1-4 1.2.2 System Integration Module (SIM)..............1-5 1.2.2.1 External Bus Interface ................1-5 1.2.2.2 Chip Select and Wait State Generation ............1-5 1.2.2.3 System Configuration and Protection ............
Page 6 CONTENTS Paragraph Page Title Number Number 2.1.1.2.3 Hardware Divide Unit ................2-14 2.1.2 Debug Module Enhancements ..............2-14 Programming Model ..................2-15 2.2.1 User Programming Model ................2-16 2.2.1.1 Data Registers (D0–D7) ................2-16 2.2.1.2 Address Registers (A0–A6) ..............2-16 2.2.1.3 Stack Pointer (A7, SP)................
Page 7 CONTENTS Paragraph Page Title Number Number 3.1.4 Data Representation..................3-5 MAC Instruction Execution Timings..............3-5 Chapter 4 Local Memory Interactions between Local Memory Modules ........... 4-1 Local Memory Registers..................4-2 SRAM Overview ....................4-2 4.3.1 SRAM Operation .................... 4-2 4.3.2 SRAM Programming Model................
Page 8 Concurrent BDM and Processor Operation ..........5-39 Processor Status, DDATA Definition............... 5-40 5.7.1 User Instruction Set ..................5-40 5.7.2 Supervisor Instruction Set................5-44 Motorola-Recommended BDM Pinout............. 5-45 Chapter 6 System Integration Module (SIM) Features ....................... 6-1 Programming Model ................... 6-3 viii...
Page 9 CONTENTS Paragraph Page Title Number Number 6.2.1 SIM Register Memory Map................6-3 6.2.2 Module Base Address Register (MBAR) ............6-4 6.2.3 System Configuration Register (SCR)............6-5 6.2.4 System Protection Register (SPR) ..............6-6 6.2.5 Power Management Register (PMR).............. 6-7 6.2.6 Activate Low-Power Register (ALPR)............
Page 10 CONTENTS Paragraph Page Title Number Number Chapter 9 SDRAM Controller Overview......................9-1 SDRAM Controller Signals ................9-1 Interface to SDRAM Devices ................9-5 SDRAM Banks, Page Hits, and Page Misses ............. 9-6 SDRAM Registers ....................9-7 9.5.1 SDRAM Configuration Register (SDCR) ............9-7 9.5.2 SDRAM Timing Register (SDTR) ..............
Page 11 CONTENTS Paragraph Page Title Number Number 11.4.4 Hash Table Algorithm .................. 11-8 11.4.5 Interpacket Gap Time ................... 11-9 11.4.6 Collision Handling..................11-9 11.4.7 Internal and External Loopback..............11-9 11.4.8 Ethernet Error-Handling Procedure ............11-10 11.4.8.1 Transmission Errors................11-10 11.4.8.2 Reception Errors ..................11-10 11.5 Programming Model ..................
Page 12 CONTENTS Paragraph Page Title Number Number Chapter 12 Universal Serial Bus (USB) 12.1 Introduction....................... 12-1 12.2 Module Operation ..................... 12-3 12.2.1 USB Module Architecture ................12-3 12.2.1.1 USB Transceiver Interface ............... 12-4 12.2.1.2 Clock Generator..................12-4 12.2.1.3 USB Control Logic ................... 12-4 12.2.1.4 Endpoint Controllers.................
Page 13 CONTENTS Paragraph Page Title Number Number 12.4.2 USB Configuration and Interface Changes ..........12-30 12.4.3 FIFO Configuration ..................12-30 12.4.4 Data Flow....................12-31 12.4.4.1 Control, Bulk, and Interrupt Endpoints ..........12-32 12.4.4.1.1 IN Endpoints..................12-32 12.4.4.1.2 OUT Endpoints................... 12-32 12.4.4.2 Isochronous Endpoints................
Page 14 CONTENTS Paragraph Page Title Number Number 13.5 PLIC Registers ....................13-16 13.5.1 B1 Data Receive Registers (P0B1RR–P3B1RR) ........13-16 13.5.2 B2 Data Receive Registers (P0B2RR–P3B2RR) ........13-17 13.5.3 D Data Receive Registers (P3DRR–P0DRR)..........13-17 13.5.4 B1 Data Transmit Registers (P3B1TR–P0B1TR) ........13-18 13.5.5 B2 Data Transmit Registers (P3B2TR–P0B2TR) ........
Page 15 CONTENTS Paragraph Page Title Number Number 14.4.1.1 Receive RAM ................... 14-5 14.4.1.2 Transmit RAM..................14-6 14.4.1.3 Command RAM..................14-6 14.4.2 Baud Rate Selection..................14-6 14.4.3 Transfer Delays..................... 14-7 14.4.4 Transfer Length..................... 14-8 14.4.5 Data Transfer ....................14-8 14.5 Programming Model ..................14-9 14.5.1 QSPI Mode Register (QMR) ................
Page 16 CONTENTS Paragraph Page Title Number Number 16.3.8 UART Input Port Change Registers (UIPCRn).......... 16-12 16.3.9 UART Auxiliary Control Registers (UACRn) ........... 16-12 16.3.10 UART Interrupt Status/Mask Registers (UISRn/UIMRn)......16-13 16.3.11 UART Divider Upper/Lower Registers (UDUn/UDLn) ......16-14 16.3.12 UART Autobaud Registers (UABUn/UABLn).......... 16-15 16.3.13 UART Transmitter FIFO Registers (UTFn) ..........
Page 17 CONTENTS Paragraph Page Title Number Number 17.2.3 Port C Control Register................. 17-8 17.2.4 Port D Control Register (PDCNT)..............17-8 17.3 Data Direction Registers ................... 17-9 17.3.1 Port A Data Direction Register (PADDR)..........17-10 17.3.2 Port B Data Direction Register (PBDDR) ..........17-10 17.3.3 Port C Data Direction Register (PCDDR) ..........
Page 18 CONTENTS Paragraph Page Title Number Number 19.6.2 DRESETEN ....................19-21 19.6.3 CPU External Clock (CLKIN)..............19-21 19.6.4 Reset Output (RSTO).................. 19-21 19.7 Interrupt Request Inputs (INT[6:1])..............19-21 19.8 General-Purpose I/O (GPIO) Ports ..............19-21 19.9 UART0 Module Signals and PB[4:0] ............. 19-22 19.9.1 Transmit Serial Data Output (URT0_TxD/PB0) ........
Page 19 Test and Debug Data In (TDI/DSI) ............19-35 19.16.5 JTAG TRST and BDM Data Clock (TRST/DSCLK) ........ 19-35 19.16.6 Motorola Test Mode Select (MTMOD)............19-35 19.16.7 Debug Transfer Error Acknowledge (TEA) ..........19-35 19.16.8 Processor Status Outputs (PST[3:0]) ............19-35 19.16.9...
Page 20 CONTENTS Paragraph Page Title Number Number 19.17 Operating Mode Configuration Pins............... 19-36 19.18 Power Supply Pins ..................19-37 Chapter 20 Bus Operation 20.1 Features ......................20-1 20.2 Bus And Control Signals .................. 20-1 20.2.1 Address Bus (A[22:0]).................. 20-2 20.2.2 Data Bus (D[31:0]) ..................20-2 20.2.3 Read/Write (R/W)..................
Page 21 CONTENTS Paragraph Page Title Number Number Chapter 22 Mechanical Data 22.1 Pinout ........................ 22-1 22.2 Package Dimensions ..................22-2 Chapter 23 Electrical Characteristics 23.1 Maximum Ratings..................... 23-1 23.1.1 Supply, Input Voltage, and Storage Temperature......... 23-1 23.1.2 Operating Temperature ................. 23-1 23.1.3 Resistance .....................
Page 22 CONTENTS Paragraph Page Title Number Number Appendix B Buffering and Impedance Matching xxii MCF5272 User’s Manual...
Page 23 ILLUSTRATIONS Figure Page Title Number Number MCF5272 Block Diagram..................... 1-2 ColdFire Pipeline ......................2-12 ColdFire Multiply-Accumulate Functionality Diagram ..........2-14 ColdFire Programming Model..................2-16 Condition Code Register (CCR) ................. 2-17 Status Register (SR)....................2-19 Vector Base Register (VBR)..................2-19 Organization of Integer Data Formats in Data Registers..........2-21 Organization of Integer Data Formats in Address Registers ........
Page 24 ILLUSTRATIONS Figure Page Title Number Number 5-20 wareg/wdreg Command Sequence................5-24 5-19 wareg/wdreg Command Format ................. 5-24 5-22 read Command Sequence.................... 5-25 5-21 read Command/Result Formats................... 5-25 5-23 write Command Format ....................5-26 5-24 write Command Sequence ..................5-27 5-25 dump Command/Result Formats ................
Page 25 ILLUSTRATIONS Figure Page Title Number Number Chip Select Base Registers (CSBRn) ................8-3 Chip Select Option Registers (CSORn)............... 8-5 SDRAM Controller Signals ..................9-2 54-Pin TSOP SDRAM Pin Definition ................9-4 SDRAM Configuration Register (SDCR) ..............9-7 SDRAM Timing Register (SDTR) ................9-9 Example Setup Time Violation on SDRAM Data Input during Write.......
Page 26 ILLUSTRATIONS Figure Page Title Number Number 11-22 Hash Table Low (HASH_TABLE_LOW) .............. 11-28 11-23 Pointer to Receive Descriptor Ring (R_DES_START)..........11-29 11-24 Pointer to Transmit Descriptor Ring (X_DES_START) .......... 11-29 11-25 Receive Buffer Size (R_BUFF_SIZE)..............11-30 11-26 Receive Buffer Descriptor (RxBD) ................11-34 11-27 Transmit Buffer Descriptor (TxBD) .................
Page 27 ILLUSTRATIONS Figure Page Title Number Number 13-13 B1 Receive Data Registers P0B1RR–P3B1RR ............13-17 13-14 B2 Receive Data Registers P3B2RR – P0B2RR ............13-17 13-15 D Receive Data Registers P3DRR–P0DRR ............. 13-18 13-16 B1 Transmit Data Registers P3B1TR–P0B1TR ............13-18 13-17 B2 Transmit Data Registers P3B2TR–P0B2TR ............
Page 28 ILLUSTRATIONS Figure Page Title Number Number 15-4 Timer Capture Registers (TCR0–TCR3) ..............15-5 15-5 Timer Counter (TCN0–TCN3) ................... 15-5 15-6 Timer Event Registers (TER0–TER3)................ 15-5 16-1 Simplified Block Diagram ..................16-1 16-2 UART Mode Registers 1 (UMR1n)................16-5 16-3 UART Mode Register 2 (UMR2n) ................16-6 16-4 UART Status Registers (USRn)..................
Page 29: Pinout
ILLUSTRATIONS Figure Page Title Number Number 18-3 PWM Width Register (PWWDn) ................18-4 18-4 PWM Waveform Examples (PWCRn[EN] = 1)............18-5 20-1 Internal Operand Representation ................20-6 20-2 MCF5272 Interface to Various Port Sizes ..............20-7 20-3 Longword Read; EBI = 00; 32-Bit Port; Internal Termination ........ 20-11 20-4 Word Write;...
Page 30 ILLUSTRATIONS Figure Page Title Number Number 23-6 Reset and Mode Select/HIZ Configuration Timing..........23-11 23-7 Real-Time Trace AC Timing ..................23-12 23-8 BDM Serial Port AC Timing ..................23-12 23-9 SDRAM Signal Timing .................... 23-14 23-10 SDRAM Self-Refresh Cycle Timing ................ 23-15 23-11 MII Receive Signal Timing Diagram ...............
Page 31 TABLES Table Page Title Number Number CCR Field Descriptions ..................... 2-17 MOVEC Register Map ....................2-18 Status Field Descriptions .................... 2-19 Integer Data Formats....................2-20 ColdFire Effective Addressing Modes................ 2-23 Notational Conventions ....................2-24 User-Mode Instruction Set Summary ................. 2-26 Supervisor-Mode Instruction Set Summary..............
Page 32 TABLES Table Page Title Number Number ABLR Field Description ....................5-9 ABHR Field Description....................5-9 CSR Field Descriptions ....................5-10 DBR Field Descriptions....................5-12 5-10 DBMR Field Descriptions ..................5-12 5-11 Access Size and Operand Data Location ..............5-12 5-12 PBR Field Descriptions ....................
Page 33 TABLES Table Page Title Number Number Connecting BS[3:0] to DQMx ..................9-4 Configurations for 16-Bit Data Bus................9-5 Configurations for 32-Bit Data Bus................9-5 Internal Address Multiplexing (16-Bit Data Bus) ............9-5 Internal Address Multiplexing (32-Bit Data Bus) ............9-6 SDCR Field Descriptions....................
Page 34 TABLES Table Page Title Number Number 11-27 R_DES_START Field Descriptions ................. 11-29 11-28 X_DES_START Field Descriptions ................. 11-30 11-29 R_BUFF_SIZE Field Descriptions ................11-30 11-30 Hardware Initialization ..................... 11-31 11-31 I ETHER_EN = 0...................... 11-31 11-32 User Initialization Process (before ETHER_EN) ............. 11-31 11-33 User Initialization (after ETHER_EN) ..............
Page 35 TABLES Table Page Title Number Number 13-15 PDRQR Field Descriptions..................13-33 13-16 P0SDR–P3SDR Field Descriptions ................13-34 13-17 PCSR Field Descriptions ..................13-35 14-1 QSPI Input and Output Signals and Functions ............14-3 14-2 QSPI_CLK Frequency as Function of CPU Clock and Baud Rate ......14-7 14-3 QMR Field Descriptions ...................
Page 36 TABLES Table Page Title Number Number 19-3 Byte Strobe Operation for 32-Bit Data Bus.............. 19-18 19-4 Byte Strobe Operation for 16-Bit Data Bus.............. 19-18 19-5 Connecting BS[3:0] to DQMx .................. 19-19 19-6 Processor Status Encoding..................19-35 19-7 MCF5272 Bus Width Selection ................19-36 19-8 MCF5272 CS0 Memory Bus Width Selection ............
Page 37 TABLES Table Page Title Number Number Interrupt Control Register Memory Map..............A-3 Chip Select Register Memory Map................A-3 GPIO Port Register Memory Map ................A-3 QSPI Module Memory Map ..................A-4 PWM Module Memory Map ..................A-4 DMA Module Memory Map..................A-4 A-10 UART0 Module Memory Map ..................
Page 38 TABLES Table Page Title Number Number xxxviii MCF5272 User’s Manual...
Page 39: Overview
To locate any published errata or updates for this document, refer to the world-wide web at http://www.motorola.com/coldﬁre. Audience This manual is intended for system software and hardware developers and applications programmers who want to develop products with the MCF5272.
Page 40: Coldfire Core
Organization — Section 4.3, “SRAM Overview,” describes the MCF5272 on-chip static RAM (SRAM) implementation. It covers general operations, conﬁguration, and initialization. It also provides information and examples of how to minimize power consumption when using the SRAM. — Section 4.4, “ROM Overview,” describes the MCF5272 on-chip static ROM. The ROM module contains tabular data that the ColdFire core can access in a single cycle.
Page 41 Organization The USB Speciﬁcation, Revision 1.1 is a recommended supplement to this chapter. It can be downloaded from http://www.usb.org. Chapter 2 of this speciﬁcation, Terms and Abbreviations, provides deﬁnitions of many of the words found here. • Chapter 13, “Physical Layer Interface Controller (PLIC),” provides detailed information about the MCF5272’s physical layer interface controller, a module intended to support ISDN applications.
Page 42 MCF5272. Because additional speeds may have become available since the publication of this book, consult Motorola’s ColdFire web page, http://www.motorola.com/coldﬁre, to conﬁrm that this is the latest information. This manual includes the following two appendixes: •...
Page 43 — ColdFire MCF5407 User’s Manual (MCF5407UM/AD) • ColdFire Programmers Reference Manual, R1.0 (MCF5200PRM/AD) • Using Microprocessors and Microcomputers: The Motorola Family, William C. Wray, Ross Bannatyne, Joseph D. Greenﬁeld Additional literature on ColdFire implementations is being released as new processors become available.
Page 44 Acronyms and Abbreviations Acronyms and Abbreviations Table i lists acronyms and abbreviations used in this document. Table i. Acronyms and Abbreviated Terms Term Meaning Analog-to-digital conversion Arithmetic logic unit AVEC Autovector Background debug mode BIST Built-in self test BSDL Boundary-scan description language CODEC Code/decode Digital-to-analog conversion...
Page 45 Acronyms and Abbreviations Table i. Acronyms and Abbreviated Terms (Continued) Term Meaning No operation Operand execution pipeline Program counter PCLK Processor clock PLIC Physical layer interface controller Phase-locked loop PLRU Pseudo least recently used Power-on reset PQFP Plastic quad ﬂat pack Pulse width modulation QSPI Queued serial peripheral interface...
Page 46 Terminology Conventions Terminology Conventions Table ii shows terminology conventions used throughout this document. Table ii Notational Conventions Instruction Operand Syntax Opcode Wildcard Logical condition (example: NE for not equal) Register Speciﬁcations Any address register n (example: A3 is address register 3) Ay,Ax Source and destination address registers, respectively Any data register n (example: D5 is data register 5)
Page 47 Terminology Conventions Table ii Notational Conventions (Continued) Instruction Operand Syntax Data cache Instruction cache # <vector> Identiﬁes the 4-bit vector number for trap instructions <> identiﬁes an indirect data address referencing memory <xxx> identiﬁes an absolute address referencing memory Signal displacement value, n bits wide (example: d16 is a 16-bit displacement) Scale factor (x1, x2, x4 for indexed addressing mode, <<1n>>...
Page 48 Terminology Conventions Table ii Notational Conventions (Continued) Instruction Operand Syntax Subﬁelds and Qualiﬁers Optional operation Identiﬁes an indirect address Displacement value, n-bits wide (example: d is a 16-bit displacement) Address Calculated effective address (pointer) Bit selection (example: Bit 3 of D0) Least signiﬁcant bit (example: lsb of D0) Least signiﬁcant byte Least signiﬁcant word...
Page 49: Overview
Chapter 1 Overview This chapter provides an overview of the MCF5272 microprocessor features, including the major functional components. 1.1 MCF5272 Key Features A block diagram of the MCF5272 is shown in Figure 1-1. The main features are as follows: • Static Version 2 ColdFire variable-length RISC processor —...
Page 50 MCF5272 Key Features V2 ColdFire Processor Complex Instruction Unit JTAG Instruction Address Generation Instruction Fetch FIFO Instruction Buffer (3 X 32) D[31:0] Decode, Select, Operand Fetch Address Generation, Execute Local Memory SRAM Controller 4-Kbyte RAMBAR SRAM ROM Controller Local 16-Kbyte ROMBAR Memory Instruction...
Page 51 MCF5272 Key Features • Ethernet Module — 10 baseT capability, half- or full-duplex — 100 baseT capability, half duplex and limited throughput full-duplex (MCF5272) — On-chip transmit and receive FIFOs — Off-chip ﬂexible buffer descriptor rings — Media-independent interface (MII) •...
Page 52: Mcf5272 Architecture
MCF5272 Architecture • System integration module (SIM) — System conﬁguration including internal and external address mapping — System protection by hardware watchdog — Versatile programmable chip select signals with wait state generation logic — Up to three 16-bit parallel input/output ports —...
Page 53: System Integration Module (Sim)
MCF5272 Architecture The Version 2 ColdFire core has a 32-bit address bus and a 32-bit data bus. The address bus allows direct addressing of up to 4 Gbytes. It supports misaligned data accesses and a bus arbitration unit for multiple bus masters. The Version 2 ColdFire supports an enhanced subset of the 68000 instruction set.
Page 54: Power Management
MCF5272 Architecture A software watchdog timer is also provided for system protection. If programmed, the timer causes a reset to the MCF5272 if it is not refreshed periodically by software. 1.2.2.4 Power Management The sleep and stop power management modes reduce power consumption by allowing software to shut down the core, peripherals, or the whole device during inactive periods.
Page 55: Timer Module
System Design to 2 stop bits in 1/16-bit increments. Receive and transmit FIFOs minimize CPU service calls. A wide variety of error detection and maskable interrupt capability is provided. Using a programmable prescaler or an external source, the MCF5272 system clock supports various baud rates.
Page 56: Mcf5272-Specific Features
MCF5272-Speciﬁc Features for chip select 0 (CS0), which is active after power-on reset until programmed otherwise. BUSW1 and BUSW0 select the initial data bus width for CS0 only. A wake-up from sleep mode or a restart from stop mode does not require reconﬁguration of the chip select registers or other system conﬁguration registers.
Page 57: Universal Serial Bus (Usb) Module
MCF5272-Speciﬁc Features • Supports transfer sizes of 8 to 16 bits in 1-bit increments • Four peripheral chip-select lines for control of up to 15 devices • Baud rates from 129.4 Kbps to 33 Mbps at 66 MHz. • Programmable delays before and after transfers •...
Page 58 MCF5272-Speciﬁc Features 1-10 MCF5272 User’s Manual...
Page 59: Coldfire Core
Chapter 2 ColdFire Core This chapter provides an overview of the microprocessor core of the MCF5272. The chapter describes the V2 programming model as it is implemented on the MCF5272. It also includes a full description of exception handling, data formats, an instruction set summary, and a table of instruction timings.
Page 60: Instruction Fetch Pipeline (Ifp)
Features and Enhancements — Instruction fetch cycle (IC) initiates prefetch on the processor’s local instruction bus. — Instruction buffer (IB) optional stage uses FIFO queue to minimize effects of fetch latency. • Two-stage OEP — Decode, select/operand fetch (DSOC) decodes the instruction and selects the required components for the effective address calculation, or the operand fetch cycle.
Page 61: Operand Execution Pipeline (Oep)
Features and Enhancements 2.1.1.2 Operand Execution Pipeline (OEP) The OEP is a two-stage pipeline featuring a traditional RISC datapath with a register ﬁle feeding an arithmetic/logic unit (ALU). For simple register-to-register instructions, the ﬁrst stage of the OEP performs the instruction decode and fetching of the required register operands (OC), while the actual instruction execution is performed in the second stage (EX).
Page 62: Hardware Divide Unit
Features and Enhancements Operand Y Operand X Shift 0,1,-1 Accumulator Figure 2-2. ColdFire Multiply-Accumulate Functionality Diagram The MAC provides functionality in the following three related areas, which are described in detail in Chapter 3, “Hardware Multiply/Accumulate (MAC) Unit.” • Signed and unsigned integer multiplies •...
Page 63: Programming Model
Programming Model — Data operand address breakpoint registers (ABHR/ABLR) — Data breakpoint register (DBR) • Data breakpoint mask register (DBMR) • Trigger deﬁnition register (TDR) can be programmed to generate a processor halt or initiate a debug interrupt exception. These registers can be accessed through the dedicated debug serial communication channel, or from the processor’s supervisor programming model, using the WDEBUG instruction.
Page 64: User Programming Model
Programming Model Data registers Address registers Stack pointer Program counter Condition code register MACSR MAC status register MAC accumulator MASK MAC mask register (CCR) Status register Must be zeros Vector base register CACR Cache control register ACR0 Access control register 0 ACR1 Access control register 1 ROMBAR...
Page 65: Stack Pointer (A7, Sp)
Programming Model 2.2.1.3 Stack Pointer (A7, SP) The processor core supports a single hardware stack pointer (A7) used during stacking for subroutine calls, returns, and exception handling. The stack pointer is implicitly referenced by certain operations and can be explicitly referenced by any instruction specifying an address register.
Page 66: Mac Programming Model
Programming Model 2.2.1.6 MAC Programming Model Figure 2-3 shows the registers in the MAC portion of the user programming model. These registers are described as follows: • Accumulator (ACC)—This 32-bit, read/write, general-purpose register is used to accumulate the results of MAC operations. •...
Page 67: Vector Base Register (Vbr)
Programming Model System byte Condition code register (CCR) Field — — — Reset — — — — — R/W R/W Figure 2-5. Status Register (SR) Table 2-3 describes SR ﬁelds. Table 2-3. Status Field Descriptions Bits Name Description Trace enable. When T is set, the processor performs a trace exception after every instruction. Supervisor/user state.
Page 68: Access Control Registers (Acr0–Acr1)
Integer Data Formats 2.2.2.4 Access Control Registers (ACR0–ACR1) The access control registers (ACR0–ACR1) deﬁne attributes for two user-deﬁned memory regions. Attributes include deﬁnition of cache mode, write protect and buffer write enables. See Section 4.5.3.2, “Access Control Registers (ACR0 and ACR1).” 2.2.2.5 ROM Base Address Register (ROMBAR) The ROMBAR base address register determines the base address of the internal ROM module and indicates the types of references mapped to it.
Page 69: Organization Of Integer Data Formats In Registers
Figure 2-8. Organization of Integer Data Formats in Address Registers The size of control registers varies according to function. Some have undeﬁned bits reserved for future deﬁnition by Motorola. Those particular bits read as zeros and must be written as zeros for future compatibility.
Page 70: Organization Of Integer Data Formats In Memory
Addressing Mode Summary 2.4.2 Organization of Integer Data Formats in Memory All ColdFire processors use a big-endian addressing scheme. The byte-addressable organization of memory allows lower addresses to correspond to higher order bytes. The address N of a longword data item corresponds to the address of the high-order word. The lower order word is located at address N + 2.
Page 71: Instruction Set Summary
Instruction Set Summary Table 2-5. ColdFire Effective Addressing Modes Category Mode Reg. Addressing Modes Syntax Field Field Data Memory Control Alterable Register direct Data reg. no. — — Address reg. no. — — — Register indirect Address (An) reg. no. Address with (An)+ reg.
Page 72 Instruction Set Summary Table 2-6. Notational Conventions Instruction Operand Syntax Opcode Wildcard Logical condition (example: NE for not equal) Register Speciﬁcations Any address register n (example: A3 is address register 3) Ay,Ax Source and destination address registers, respectively Any data register n (example: D5 is data register 5) Dy,Dx Source and destination data registers, respectively Any control register (example VBR is the vector base register)
Page 73 Instruction Set Summary Table 2-6. Notational Conventions (Continued) Instruction Operand Syntax Signal displacement value, n bits wide (example: d16 is a 16-bit displacement) Scale factor (x1, x2, x4 for indexed addressing mode, <<1n>> for MAC operations) Operations Arithmetic addition or postincrement indicator –...
Page 74: Instruction Set Summary
Instruction Set Summary Table 2-6. Notational Conventions (Continued) Instruction Operand Syntax Condition Code Register Bit Names Carry Negative Overﬂow Extend Zero 2.6.1 Instruction Set Summary Table 2-7 lists implemented user-mode instructions by opcode. Table 2-7. User-Mode Instruction Set Summary Instruction Operand Syntax Operand Size Operation...
Page 75 Instruction Set Summary Table 2-7. User-Mode Instruction Set Summary (Continued) Instruction Operand Syntax Operand Size Operation CMPA <ea>y,Dx Destination – source CMPI <ea>y,Dx Destination – immediate data DIVS <ea-1>y,Dx Dx /<ea>y → Dx {16-bit remainder; 16-bit quotient} <ea>y,Dx Dx /<ea>y → Dx {32-bit quotient} Signed operation DIVU <ea-1>y,Dx...
Page 76 Instruction Set Summary Table 2-7. User-Mode Instruction Set Summary (Continued) Instruction Operand Syntax Operand Size Operation MOVEA <ea>y,Ax .W,.L → .L Source → destination MOVEM #<list>,<ea-2>x Listed registers → destination <ea-2>y,#<list> Source → listed registers MOVEQ #<data>,Dx .B → .L Sign-extended immediate data →...
Page 77: Instruction Timing
Instruction Timing Table 2-7. User-Mode Instruction Set Summary (Continued) Instruction Operand Syntax Operand Size Operation TRAPF None Unsized PC + 2 → PC #<data> PC + 4 → PC PC + 6 → PC <ea>y .B,.W,.L Set condition codes UNLK Unsized Ax →SP;...
Page 78: Move Instruction Execution Times
Instruction Timing certain hardware resources within the processor are marked as busy for two clock cycles after the ﬁnal DSOC cycle of the store instruction. If a subsequent store instruction is encountered within this two-cycle window, it is stalled until the resource again becomes available.
Page 79 Instruction Timing Table 2-10 lists execution times for MOVE.{B,W} instructions. Table 2-10. Move Byte and Word Execution Times Destination Source (Ax) (Ax)+ -(Ax) (d16,Ax) (d8,Ax,Xi*SF) (xxx).wl 1(0/0) 1(0/1) 1(0/1) 1(0/1) 1(0/1) 2(0/1) 1(0/1) 1(0/0) 1(0/1) 1(0/1) 1(0/1) 1(0/1) 2(0/1) 1(0/1) (Ay) 3(1/0) 3(1/1)
Page 80: Execution Timings—One-Operand Instructions
Instruction Timing MAC execution pipeline. In general, these store operations require only one cycle for execution, but if they are preceded immediately by a load, MAC, or MSAC instruction, the MAC pipeline depth is exposed and execution time is three cycles. Table 2-12.
Page 81: Execution Timings—Two-Operand Instructions
Instruction Timing 2.7.3 Execution Timings—Two-Operand Instructions Table 2-14 shows standard timings for two-operand instructions. Table 2-14. Two-Operand Instruction Execution Times Effective Address Opcode <ea> (An) (An)+ -(An) (d16,An) (d8,An,Xi*SF) (xxx).wl #<xxx> add.l <ea>,Rx 1(0/0) 3(1/0) 3(1/0) 3(1/0) 3(1/0) 4(1/0) 3(1/0) 1(0/0) add.l Dy,<ea>...
Page 82: Miscellaneous Instruction Execution Times
Instruction Timing Table 2-14. Two-Operand Instruction Execution Times (Continued) Effective Address Opcode <ea> (An) (An)+ -(An) (d16,An) (d8,An,Xi*SF) (xxx).wl #<xxx> msac.l Ry,Rx 3(0/0) — — — — — — — mac.w Ry,Rx,ea,Rw — 3(1/0) 3(1/0) 3(1/0) 3(1/0) — — — mac.l Ry,Rx,ea,Rw —...
Page 83: Branch Instruction Execution Times
Instruction Timing Table 2-15. Miscellaneous Instruction Execution Times (Continued) Effective Address Opcode <ea> (An) (An)+ -(An) (d16,An) (d8,An,Xi*SF) (xxx).wl #<xxx> movem.l <ea>,&list — 1+n(n/0) — — 1+n(n/0) — — — movem.l &list,<ea> — 1+n(0/n) — — 1+n(0/n) — — — 3(0/0) —...
Page 84: Exception Processing Overview
Exception Processing Overview Table 2-17. Bcc Instruction Execution Times Forward Not Backward Not Opcode Forward Taken Backward Taken Taken Taken 3(0/0) 1(0/0) 2(0/0) 3(0/0) 2.8 Exception Processing Overview Exception processing for ColdFire processors is streamlined for performance. Differences from previous M68000 Family processors include the following: •...
Page 85 ColdFire processors support a 1024-byte vector table aligned on any 1-Mbyte address boundary; see Table 2-18. The table contains 256 exception vectors where the ﬁrst 64 are deﬁned by Motorola; the remaining 192 are user-deﬁned interrupt vectors. Table 2-18. Exception Vector Assignments...
Page 86 Exception Processing Overview 2.8.1 Exception Stack Frame Deﬁnition The exception stack frame is shown in Figure 2-10. The ﬁrst longword of the exception stack frame contains the 16-bit format/vector word (F/V) and the 16-bit status register. The second longword contains the 32-bit program counter address. A7→...
Page 87: Processor Exceptions
Exception Processing Overview • Vector number—This 8-bit ﬁeld, vector[7–0], deﬁnes the exception type. It is calculated by the processor for internal faults and is supplied by the peripheral for interrupts. See Table 2-18. 2.8.2 Processor Exceptions Table 2-21 describes MCF5272 exceptions. Table 2-21.
Page 88 Exception Processing Overview Table 2-21. MCF5 Exceptions (Continued) Exception Description Trace ColdFire processors provide instruction-by-instruction tracing. While the processor is in trace mode Exception (SR[T] = 1), instruction completion signals a trace exception. This allows a debugger to monitor program execution. The only exception to this deﬁnition is the STOP instruction.
Page 89 Exception Processing Overview Table 2-21. MCF5 Exceptions (Continued) Exception Description Interrupt Interrupt exception processing, with interrupt recognition and vector fetching, includes uninitialized Exception and spurious interrupts as well as those where the requesting device supplies the 8-bit interrupt vector. Reset Asserting the reset input signal (RSTI) causes a reset exception.
Page 90 Exception Processing Overview 2-42 MCF5272 User’s Manual...
Page 91: Hardware Multiply/Accumulate (Mac) Unit
Chapter 3 Hardware Multiply/Accumulate (MAC) Unit This chapter describes the MCF5272 multiply/accumulate (MAC) unit, which executes integer multiply, multiply-accumulate, and miscellaneous register instructions. The MAC is integrated into the operand execution pipeline (OEP). 3.1 Overview The MAC unit provides hardware support for a limited set of digital signal processing (DSP) operations used in embedded code, while supporting the integer multiply instructions in the ColdFire microprocessor family.
Page 92: Mac Programming Model
Overview Operand Y Operand X Shift 0,1,-1 Accumulator Figure 3-1. ColdFire MAC Multiplication and Accumulation The MAC unit is an extension of the basic multiplier found on most microprocessors. It can perform operations native to signal processing algorithms in an acceptable number of cycles, given the application constraints.
Page 93: General Operation
Overview These registers are described as follows: • Accumulator (ACC)—This 32-bit, read/write, general-purpose register is used to accumulate the results of MAC operations. • Mask register (MASK)—This 16-bit general-purpose register provides an optional address mask for MAC instructions that fetch operands from memory. It is useful in the implementation of circular queues in operand memory.
Page 94: Mac Instruction Set Summary
Overview The need to move large amounts of data quickly can limit throughput in DSP engines. However, data can be moved efﬁciently by using the MOVEM instruction, which automatically generates line-sized burst references and is ideal for ﬁlling registers quickly with input data, ﬁlter coefﬁcients, and output data.
Page 95: Data Representation
MAC Instruction Execution Timings 3.1.4 Data Representation The MAC unit supports three basic operand types: • Two’s complement signed integer: In this format, an N-bit operand represents a (N-1) (N-1) number within the range -2 < operand < 2 - 1. The binary point is to the right of the least signiﬁcant bit.
Page 96 MAC Instruction Execution Timings MCF5272 User’s Manual...
Page 97: Local Memory
Chapter 4 Local Memory This chapter describes the MCF5272 implementation of the ColdFire Version 2 core local memory speciﬁcation. It consists of the following sections. • Section 4.3, “SRAM Overview,” and Section 4.4, “ROM Overview,” describe the on-chip static RAM (SRAM) and ROM implementations. These chapters cover general operations, conﬁguration, and initialization.
Page 98: Local Memory Registers
Local Memory Registers 4.2 Local Memory Registers Table 4-1 lists the local memory registers. Note the following: • Addresses not assigned to the register and undeﬁned register bits are reserved. Write accesses to these bits have no effect; read accesses return zeros. •...
Page 99: Sram Base Address Register (Rambar)
SRAM Overview 4.3.2.1 SRAM Base Address Register (RAMBAR) RAMBAR determines the base address location of the internal SRAM module, as well as the deﬁnition of the types of accesses allowed for it. • RAMBAR is a 32-bit write-only supervisor control register. It is accessed in the CPU address space via the MOVEC instruction with an Rc encoding of 0xC04.
Page 100: Sram Initialization
SRAM Overview Table 4-2. RAMBAR Field Description (Continued) Bits Name Description 5–1 C/I, Address space masks (ASn). These ﬁelds allow certain types of accesses to be masked, or inhibited from accessing the SRAM module. These bits are useful for power management as described in Section 4.3.2.3, “Programming RAMBAR for Power Management.”...
Page 101: Programming Rambar For Power Management
ROM Overview 4.3.2.3 Programming RAMBAR for Power Management Depending on the conﬁguration deﬁned by RAMBAR, instruction fetch accesses can be sent to the SRAM module, ROM module, and instruction cache simultaneously. If the access is mapped to the SRAM module, it sources the read data, discarding the instruction cache access.
Page 102: Rom Programming Model
ROM Overview 4.4.2 ROM Programming Model The MCF5272 implements the ROM base address register (ROMBAR), shown in Figure 4-2 and described in the following section. 4.4.2.1 ROM Base Address Register (ROMBAR) ROMBAR determines the base address location of the internal ROM module, as well as the deﬁnition of the allowable access types.
Page 103: Programming Rombar For Power Management
Instruction Cache Overview 4.4.2.2 Programming ROMBAR for Power Management Depending on the ROMBAR conﬁguration, memory accesses can be sent to the ROM module and the cache simultaneously. If an access hits both, the ROM module sources read data and the instruction cache access is discarded. Because the ROM contains only for data, setting ROMBAR[SC,UC] lowers power dissipation by disabling the ROM during instruction fetches.
Page 104 Instruction Cache Overview The tag array maintains a single valid bit per line entry. Accordingly, only entire 16-byte lines are loaded into the instruction cache. The instruction cache also contains a 16-byte ﬁll buffer that provides temporary storage for the last line fetched in response to a cache miss. With each instruction fetch, the contents of the line-ﬁll buffer are examined.
Page 105: Instruction Cache Operation
Instruction Cache Overview 4.5.2 Instruction Cache Operation The instruction cache is physically connected to the ColdFire core's local bus, allowing it to service all instruction fetches from the ColdFire core and certain memory fetches initiated by the debug module. Typically, the debug module's memory references appear as supervisor data accesses but the unit can be programmed to generate user-mode accesses and/or instruction fetches.
Page 106: Cacheable Accesses
Instruction Cache Overview else if (address == ACR1-address including mask) effective attributes = ACR1 attributes else effective attributes = CACR default attributes Addresses matching an ACR can also be write-protected using ACR[WP]. Reset disables the cache and clears all CACR bits. Reset does not automatically invalidate cache entries;...
Page 107: Reset
Instruction Cache Overview In this case, a fetched line is stored in the ﬁll buffer and remains valid there; the cache can service additional read accesses from this buffer until another ﬁll occurs or a cache-invalidate-all operation occurs. If ACRn[CM] indicates cache-inhibited, the controller bypasses the cache and performs an external transfer.
Page 108: Instruction Cache Programming Model
Instruction Cache Overview to the cache location deﬁned by bits 9–4 of the ﬁll buffer address, the data in the cache memory array is now most-recently used, so the hardware indicator is cleared. In all cases, the indicator deﬁnes whether the contents of the line-ﬁll buffer or the cache memory data array are most recently used.
Page 109: Cache Control Register (Cacr)
Instruction Cache Overview • The access column indicates whether the corresponding register can be read, written or both. Attempts to read a write-only register cause zeros to be returned. Attempts to write to a read-only register are ignored. Table 4-7. Memory Map of Instruction Cache Registers Address (using MOVEC) Name Width Description Reset Value...
Page 110 Instruction Cache Overview Table 4-8. CACR Field Descriptions (Continued) Bits Name Description CFRZ Cache freeze. Allows the user to freeze the contents of the cache. When CFRZ is asserted line fetches can be initiated and loaded into the line-ﬁll buffer, but a valid cache entry can not be overwritten.
Page 111: Access Control Registers (Acr0 And Acr1)
Instruction Cache Overview Table 4-8. CACR Field Descriptions (Continued) Bits Name Description 1–0 CLNF Control longword fetch. Controls the size of the memory request the cache issues to the bus controller for different initial line access offsets. Longword Address Bits CLNF Line Line...
Page 112 Instruction Cache Overview Table 4-9. ACRn Field Descriptions (Continued) Bits Name Description 14–13 Supervisor mode. Speciﬁes whether only user or supervisor accesses are allowed in this address range or if the type of access is a don’t care. 00 Match addresses only in user mode 01 Match addresses only in supervisor mode 1x Execute cache matching on all accesses 12–7...
Page 113: Debug Support
Chapter 5 Debug Support This chapter describes the Revision A enhanced hardware debug support in the MCF5272. 5.1 Overview The debug module is shown in Figure 5-1. High-speed ColdFire CPU Core local bus Debug Module Control Trace Port Communication Port PST[3:0], DDATA[3:0] BKPT DSCLK, DSI, DSO...
Page 114: Signal Description
Table 5-1 describes debug module signals. All ColdFire debug signals are unidirectional and related to a rising edge of the processor core’s clock signal. The standard 26-pin debug connector is shown in Section 5.8, “Motorola-Recommended BDM Pinout.” Table 5-1. Debug Module Signals...
Page 115 Real-Time Trace Support the other allows operand data to be displayed (debug data, DDATA). The processor status may not be related to the current bus transfer. External development systems can use PST outputs with an external image of the program to completely track the dynamic execution path.
Page 116: Begin Execution Of Taken Branch (Pst = 0X5)
Real-Time Trace Support Table 5-2. Processor Status Encoding PST[3:0] Deﬁnition Binary 0000 Continue execution. Many instructions execute in one processor cycle. If an instruction requires more clock cycles, subsequent clock cycles are indicated by driving PST outputs with this encoding. 0001 Begin execution of one instruction.
Page 117: Programming Model
Programming Model Bytes are displayed in least-to-most-signiﬁcant order. The processor captures only those target addresses associated with taken branches which use a variant addressing mode, that is, RTE and RTS instructions, JMP and JSR instructions using address register indirect or indexed addressing modes, and all exception vectors.
Page 118 Programming Model development system using the debug serial interface or by the operating system running on the processor core. Software is responsible for guaranteeing that accesses to these resources are serialized and logically consistent. Hardware provides a locking mechanism in the CSR to allow the external development system to disable any attempted writes by the processor to the breakpoint registers (setting CSR[IPW]).
Page 119: Revision A Shared Debug Resources
Programming Model Table 5-3. BDM/Breakpoint Registers (Continued) DRc[4–0] Register Name Abbreviation Initial State Page 0x09 Program counter breakpoint mask register PBMR — p. 5-12 0x0A–0x0B Reserved — — — 0x0C Address breakpoint high register ABHR — p. 5-9 0x0D Address breakpoint low register ABLR —...
Page 120 Programming Model Field RM Reset 0000_0000_0000_0101 R/W Write only. AATR is accessible in supervisor mode as debug control register 0x06 using the WDEBUG instruction and through the BDM port using the command. WDMREG DRc[4–0] 0x06 Figure 5-5. Address Attribute Trigger Register (AATR) Table 5-5 describes AATR fields Table 5-5.
Page 121: Address Breakpoint Registers (Ablr, Abhr)
Programming Model 5.4.3 Address Breakpoint Registers (ABLR, ABHR) The address breakpoint low and high registers (ABLR, ABHR), Figure 5-6, deﬁne regions in the processor’s data address space that can be used as part of the trigger. These register values are compared with the address for each transfer on the processor’s high-speed local bus.
Page 122: Configuration/Status Register (Csr)
R/W R/W R/W R/W R/W R/W R/W — DRc[4–0] 0x00 Bit 7 is reserved for Motorola use and must be written as a zero. Figure 5-7. Configuration/Status Register (CSR) Table 5-8 describes CSR ﬁelds. Table 5-8. CSR Field Descriptions Name Description 31–28...
Page 123: Data Breakpoint/Mask Registers (Dbr, Dbmr)
Programming Model Table 5-8. CSR Field Descriptions (Continued) Name Description Force emulation mode. If EMU = 1, the processor begins executing in emulator mode. See Section 5.6.1.1, “Emulator Mode.” 12–11 Debug data control. Controls operand data capture for DDATA, which displays the number of bytes deﬁned by the operand reference size before the actual data;...
Page 124: Program Counter Breakpoint/Mask Registers (Pbr, Pbmr)
Programming Model Field Data (DBR); Mask (DBMR) Reset Uninitialized R/W DBR is accessible in supervisor mode as debug control register 0x0E, using the WDEBUG instruction and through the BDM port using the commands. RDMREG WDMREG DBMR is accessible in supervisor mode as debug control register 0x0F,using the WDEBUG instruction and via the BDM port using the command.
Page 125 Programming Model when TDR is conﬁgured appropriately. PBR bits are masked by setting corresponding PBMR bits. Results are compared with the processor’s program counter register, as deﬁned in TDR. Figure 5-9 shows the PC breakpoint register. Field Program Counter Reset —...
Page 126: Trigger Definition Register (Tdr)
Programming Model NOTE: The debug module has no hardware interlocks, so to prevent spurious breakpoint triggers while the breakpoint registers are being loaded, disable TDR (by clearing TDR[29,13])before deﬁning triggers. A write to TDR clears the CSR trigger status bits, CSR[BSTAT]. Second-Level Trigger Field EDLW EDWL EDWU EDLL EDLM EDUM EDUU...
Page 127: Background Debug Mode (Bdm)
Background Debug Mode (BDM) Table 5-14. TDR Field Descriptions (Continued) Bits Name Description 28–22 Setting an EDx bit enables the corresponding data breakpoint condition based on the size and 12–6 placement on the processor’s local data bus. Clearing all EDx bits disables data breakpoints. 28/12 Data longword.
Page 128: Cpu Halt
Background Debug Mode (BDM) 5.5.1 CPU Halt Although most BDM operations can occur in parallel with CPU operations, unrestricted BDM operation requires the CPU to be halted. The sources that can cause the CPU to halt are listed below in order of priority: 1.
Page 129: Bdm Serial Interface
Background Debug Mode (BDM) 5.5.2 BDM Serial Interface When the CPU is halted and PST reﬂects the halt status, the development system can send unrestricted commands to the debug module. The debug module implements a synchronous protocol using two inputs (DSCLK and DSI) and one output (DSO), where DSO is speciﬁed as a delay relative to the rising edge of the processor clock.
Page 130: Receive Packet Format
Background Debug Mode (BDM) NOTE: A not-ready response can be ignored except during a memory-referencing cycle. Otherwise, the debug module can accept a new serial transfer after 32 processor clock periods. 5.5.2.1 Receive Packet Format The basic receive packet, Figure 5-13, consists of 16 data bits and 1 status bit. Data Field [15:0] Figure 5-13.
Page 131: Bdm Command Set
- Steal. Command generates bus cycles that can be interleaved with bus accesses. - Parallel. Command is executed in parallel with CPU activity. 0x4 is a three-bit ﬁeld. Unassigned command opcodes are reserved by Motorola. All unused command formats within any revision level perform a and return the illegal command response.
Page 132: Coldfire Bdm Command Format
Background Debug Mode (BDM) 5.5.3.1 ColdFire BDM Command Format All ColdFire Family BDM commands include a 16-bit operation word followed by an optional set of one or more extension words, as shown in Figure 5-15. Operation Op Size Register Extension Word(s) Figure 5-15.
Page 133: Command Sequence Diagrams
Background Debug Mode (BDM) 5.5.3.2 Command Sequence Diagrams The command sequence diagram in Figure 5-16 shows serial bus trafﬁc for commands. Each bubble represents a 17-bit bus transfer. The top half of each bubble indicates the data the development system sends to the debug module; the bottom half indicates the debug module’s response to the previous development system commands.
Page 134: Command Set Descriptions
S = 1 for illegal commands, not-ready responses, and transfers with bus-errors. Section 5.5.2, “BDM Serial Interface,” describes the receive packet format. Motorola reserves unassigned command opcodes for future expansion. Unused command formats in any revision level perform a and return an illegal command response.
Page 135 Background Debug Mode (BDM) 5.5.3.3.1 Read A/D Register ( RAREG RDREG Read the selected address or data register and return the 32-bit result. A bus error response is returned if the CPU core is not halted. Command/Result Formats: Command Register Result D[31:16] D[15:0]...
Page 136 Background Debug Mode (BDM) 5.5.3.3.2 Write A/D Register ( WAREG WDREG The operand longword data is written to the speciﬁed address or data register. A write alters all 32 register bits. A bus error response is returned if the CPU core is not halted. Command Format: Register D[31:16]...
Page 137: Read Memory Location (Read)
Background Debug Mode (BDM) 5.5.3.3.3 Read Memory Location ( READ Read data at the longword address. Address space is deﬁned by BAAR[TT,TM]. Hardware forces low-order address bits to zeros for word and longword accesses to ensure that word addresses are word-aligned and longword addresses are longword-aligned. Command/Result Formats: Byte Command...
Page 138: Write Memory Location (Write)
Background Debug Mode (BDM) 5.5.3.3.4 Write Memory Location ( WRITE Write data to the memory location speciﬁed by the longword address. The address space is deﬁned by BAAR[TT,TM]. Hardware forces low-order address bits to zeros for word and longword accesses to ensure that word addresses are word-aligned and longword addresses are longword-aligned.
Page 139 Background Debug Mode (BDM) Command Sequence: WRITE WRITE (B/W) MS ADDR LS ADDR DATA MEMORY "NOT READY" "NOT READY" "NOT READY" "NOT READY" LOCATION NEXT CMD "CMD COMPLETE" BERR NEXT CMD "NOT READY" WRITE (LONG) MS ADDR LS ADDR MS DATA "NOT READY"...
Page 140 Background Debug Mode (BDM) 5.5.3.3.5 Dump Memory Block ( DUMP is used with the command to access large blocks of memory. An initial DUMP READ READ is executed to set up the starting address of the block and to retrieve the ﬁrst result. If an initial is not executed before the ﬁrst , an illegal command response is returned.
Page 141 Background Debug Mode (BDM) Command Sequence: READ DUMP (B/W) MEMORY "NOT READY" LOCATION NEXT CMD RESULT NEXT CMD NEXT CMD "ILLEGAL" "NOT READY" BERR "NOT READY" READ DUMP (LONG) MEMORY "NOT READY" LOCATION NEXT CMD NEXT CMD MS RESULT LS RESULT NEXT CMD NEXT CMD "ILLEGAL"...
Page 142 Background Debug Mode (BDM) 5.5.3.3.6 Fill Memory Block ( FILL command is used with the command to access large blocks of memory. An FILL WRITE initial is executed to set up the starting address of the block and to supply the ﬁrst WRITE operand.
Page 143 Background Debug Mode (BDM) Command Sequence: WRITE FILL (LONG) LS DATA FILL (B/W) MS DATA MEMORY "NOT READY" "NOT READY" "NOT READY" LOCATION NEXT CMD NEXT CMD "NOT READY" "CMD COMPLETE" "ILLEGAL" NEXT CMD "NOT READY" BERR WRITE FILL (LONG) FILL (B/W) DATA MEMORY...
Page 144 Background Debug Mode (BDM) 5.5.3.3.7 Resume Execution ( The pipeline is ﬂushed and reﬁlled before normal instruction execution resumes. Prefetching begins at the current address in the PC and at the current privilege level. If any register (such as the PC or SR) is altered by a BDM command while the processor is halted, the updated value is used when prefetching resumes.
Page 145 Background Debug Mode (BDM) 5.5.3.3.8 No Operation ( performs no operation and may be used as a null command where required. Command Formats: Figure 5-31. Command Format Command Sequence: NEXT CMD "CMD COMPLETE" Figure 5-32. Command Sequence Operand Data: None Result Data: The command-complete response, 0xFFFF (with S cleared), is returned during the next shift operation.
Page 146 Background Debug Mode (BDM) 5.5.3.3.9 Read Control Register ( RCREG Read the selected control register and return the 32-bit result. Accesses to the processor/memory control registers are always 32 bits wide, regardless of register width. The second and third words of the command form a 32-bit address, which the debug module uses to generate a special bus cycle to access the speciﬁed control register.
Page 147 Background Debug Mode (BDM) 5.5.3.3.10 Write Control Register ( WCREG The operand (longword) data is written to the speciﬁed control register. The write alters all 32 register bits. Command/Result Formats: Command Result D[31:16] D[15:0] Figure 5-35. Command/Result Formats WCREG Command Sequence: WCREG EXT WORD MS ADDR...
Page 148 Background Debug Mode (BDM) 5.5.3.3.11 Read Debug Module Register ( RDMREG Read the selected debug module register and return the 32-bit result. The only valid register selection for the command is CSR (DRc = 0x00). Note that this read of the CSR RDMREG clears CSR[FOF, TRG, HALT, BKPT];...
Page 149: Real-Time Debug Support
Real-Time Debug Support 5.5.3.3.12 Write Debug Module Register ( WDMREG The operand (longword) data is written to the speciﬁed debug module register. All 32 bits of the register are altered by the write. DSCLK must be inactive while the debug module register writes from the CPU accesses are performed using the WDEBUG instruction.
Page 150: Theory Of Operation
Real-Time Debug Support 5.6.1 Theory of Operation Breakpoint hardware can be conﬁgured to respond to triggers in several ways. The response desired is programmed into TDR. As shown in Table 5-21, when a breakpoint is triggered, an indication (CSR[BSTAT]) is provided on the DDATA output port when it is not displaying captured processor status, operands, or branch addresses.
Page 151: Emulator Mode
Real-Time Debug Support Execution continues at the instruction address in the vector corresponding to the breakpoint triggered. All interrupts are ignored while the processor is in emulator mode. The debug interrupt handler can use supervisor instructions to save the necessary context such as the state of all program-visible registers into a reserved memory area.
Page 152: User Instruction Set
Processor Status, DDATA Deﬁnition bus. The processor responds by stalling the instruction fetch pipeline and waiting for current bus activity to complete before freeing the local bus for the debug module to perform its access. After the debug module bus cycle, the processor reclaims the bus. Breakpoint registers must be carefully conﬁgured in a development system if the processor is executing.
Page 153 Processor Status, DDATA Deﬁnition Table 5-22. PST/DDATA Specification for User-Mode Instructions Instruction Operand Syntax PST/DDATA add.l <ea>y,Rx PST = 0x1, {PST = 0xB, DD = source operand} add.l Dy,<ea>x PST = 0x1, {PST = 0xB, DD = source}, {PST = 0xB, DD = destination} addi.l #imm,Dx PST = 0x1...
Page 154 Processor Status, DDATA Deﬁnition Table 5-22. PST/DDATA Specification for User-Mode Instructions (Continued) Instruction Operand Syntax PST/DDATA <ea>x PST = 0x5, {PST = [0x9AB], DD = target address}, {PST = 0x B , DD = destination operand} <ea>y,Ax PST = 0x1 link.w Ay,#imm PST = 0x1, {PST = 0xB, DD = destination operand}...
Page 155 Processor Status, DDATA Deﬁnition Table 5-22. PST/DDATA Specification for User-Mode Instructions (Continued) Instruction Operand Syntax PST/DDATA negx.l PST = 0x1 PST = 0x1 not.l PST = 0x1 or.l <ea>y,Dx PST = 0x1, {PST = 0xB, DD = source operand} or.l Dy,<ea>x PST = 0x1, {PST = 0xB, DD = source}, {PST = 0xB, DD = destination} ori.l...
Page 156: Supervisor Instruction Set
Processor Status, DDATA Deﬁnition Exception Processing PST = 0xC, {PST = 0xB,DD = destination}, // stack frame {PST = 0xB,DD = destination}, // stack frame {PST = 0xB,DD = source}, // vector read PST = 0x5, {PST = [0x9AB],DD = target} // handler PC The PST/DDATA speciﬁcation for the reset exception is shown below: Exception Processing PST = 0xC,...
Page 157: Motorola-Recommended Bdm Pinout
Motorola-Recommended BDM Pinout 5.8 Motorola-Recommended BDM Pinout The ColdFire BDM connector, Figure 5-41, is a 26-pin Berg connector arranged 2 x 13. Figure 5-41. Recommended BDM Connector Developer reserved BKPT DSCLK Developer reserved RESET Pad-Voltage PST3 PST1 PST2 DDATA3 PST0...
Page 158 Motorola-Recommended BDM Pinout 5-46 MCF5272 User’s Manual...
Page 159: System Integration Module (Sim)
Chapter 6 System Integration Module (SIM) This chapter provides detailed operation information regarding the system integration module (SIM). It describes the SIM programming model, bus arbitration, power management, and system-protection functions for the MCF5272. 6.1 Features The SIM, shown in Figure 6-1, provides overall control of the bus and serves as the interface between the ColdFire core processor complex and the internal peripheral devices.
Page 160: Interrupt Controller
Features The following is a list of the key SIM features: • Module base address register (MBAR) — Base address location of all internal peripherals, SIM resources, and memory-mapped registers — Address space masking to internal peripherals and SIM resources •...
Page 161: Programming Model
Programming Model 6.2 Programming Model The following sections describe the registers incorporated into the SIM. 6.2.1 SIM Register Memory Map Table 6-1 shows the memory map for the SIM registers. The internal registers in the SIM are memory-mapped registers offset from the MBAR address pointer deﬁned in MBAR[BA].
Page 162: Module Base Address Register (Mbar)
Programming Model 6.2.2 Module Base Address Register (MBAR) The supervisor-level MBAR, Figure 6-2, speciﬁes the base address and allowable access types for all internal peripherals. It is written with a MOVEC instruction using the CPU address 0xC0F. (See the ColdFire Family Programmer’s Reference Manual.) MBAR can be read or written through the debug module as a read/write register, as described in.”...
Page 163: System Configuration Register (Scr)
Programming Model Table 6-2. MBAR Field Descriptions Bits Field Description 31–16 Base address. Deﬁnes the base address for a 64-Kbyte address range 15–5 — Reserved, should be cleared. Setting masks supervisor code space in MBAR address range Setting masks supervisor data space in MBAR address range Setting masks user code space in MBAR address range Setting masks user data space in MBAR address range Valid.
Page 164: Sdram Controller
Programming Model Table 6-3. SCR Field Descriptions (Continued) Bits Field Description Priority Selects the bus arbiter priority scheme. 0 Ethernet has highest priority, DMA has next highest priority, CPU has lowest priority. 1 CPU has highest priority, DMA has next highest priority, Ethernet has lowest priority. This bit should be cleared if the Ethernet module is enabled.
Page 165: Power Management Register (Pmr)
Programming Model Field Reset 0000_0000 Field ADCEN WPVEN SMVEN PEEN HWTEN RPVEN EXTEN SUVEN Reset 0000_1011 Address MBAR + 0x006 Figure 6-4. System Protection Register (SPR) Table 6-4 describes SPR ﬁelds. Table 6-4. SPR Field Descriptions Bits Fields Description 15, 7 ADC, Address decode conﬂict.
Page 166: Dma Controller Module
Programming Model Field BDMPDN — ENETPDN PLIPDN DRAMPDN Reset 0000_0000 R/W, Supervisor mode only Field DMAPDN PWMPDN QSPIPDN TIMERPDN GPIOPDN USBPDN UART1PDN UART0PDN Reset 0000_0000 R/W, Supervisor mode only Field — USBWK UART1WK UART0WK Reset 0000_0000 R/W, Supervisor mode only Field —...
Page 167 Programming Model Table 6-5. PMR Field Descriptions (Continued) Bits Field Description QSPIPDN QSPI power-down enable. Controls the clocking to the QSPI module. 0 Clock enabled. 1 Clock disabled. TIMERPDN Timer power-down enable. Controls the clocking to the timer module. 0 Clock enabled. 1 Clock disabled.
Page 168: Activate Low-Power Register (Alpr)
Programming Model Table 6-5. PMR Field Descriptions (Continued) Bits Field Description SLPEN Sleep enable. Allows the MCF5272 to be put into sleep mode in which internal clocking to the CPU is disabled.To enter sleep mode, the user must write to the ALPR and then execute a STOP instruction.
Page 169 Programming Model 4. Execute the STOP instruction. This must be the next instruction executed after the write to the ALPR. Sleep mode is exited by an interrupt request from by either an external device or an on-chip peripheral as detailed in Table 6-7. The sequence to enter stop mode is: 1.
Page 170: Device Identification Register (Dir)
21–12 Device number. Indicates an MCF5272 11–1 Indicates the reduced JEDEC ID for Motorola. Joint Electron Device Engineering Council (JEDEC) Publication 106-A and Chapter 11 of the IEEE Standard 1149.1 give more information on this ﬁeld. 6.2.8 Software Watchdog Timer The software watchdog timer prevents system lockup should the software become trapped in loops with no controlled exit.
Page 171: Watchdog Reset Reference Register (Wrrr)
Programming Model 6.2.8.1 Watchdog Reset Reference Register (WRRR) The watchdog reset reference register (WRRR), Figure 6-8, contains the reference value for the software watchdog timeout causing a reset. Field Reset 1111_1111_1111_1110 Address MBAR + 0x280 Figure 6-8. Watchdog Reset Reference Register (WRRR) Table 6-9 describes WRRR ﬁelds.
Page 172: Watchdog Counter Register (Wcr)
Programming Model 6.2.8.3 Watchdog Counter Register (WCR) The WCR, Figure 6-10, contains the 16 most signiﬁcant bits of the software watchdog counter. Writing any value to WCR resets the counter and prescaler and should be executed on a regular basis if the watchdog is enabled. Field COUNT Reset...
Page 173: Ethernet Module
Chapter 7 Interrupt Controller This chapter describes the operation of the interrupt controller portion of the system integration module (SIM). It includes descriptions of the registers in the interrupt controller memory map and the interrupt priority scheme. 7.1 Overview The SIM provides a centralized interrupt controller for all MCF5272 interrupt sources, which consist of the following: •...
Page 174: Interrupt Controller Registers
Interrupt Controller Registers PLIC QSPI SYSTEM INTEGRATION MODULE (SIM) Software Watchdog Interrupt Controller Ethernet 4 ICRs Two UARTs PITR PIWR Four General- PIVR Purpose Timers INT[1:6] Figure 7-1. Interrupt Controller Block Diagram The SIM provides the following registers for managing interrupts: •...
Page 175: Interrupt Controller Registers
Interrupt Controller Registers Table 7-1. Interrupt Controller Registers 0x030 Interrupt source register (ISR) [p. 7-6] 0x034 Programmable interrupt transition register (PITR) [p. 7-8] 0x038 Programmable interrupt wakeup register (PIWR) [p. 7-9] 0x03C Reserved Programmable interrupt vector register (PIVR) [p. 7-9] All external interrupt inputs are edge sensitive, with the active edge being programmable through PITR.
Page 176: Interrupt Control Registers (Icr1–Icr4)
Interrupt Controller Registers Table 7-2. Interrupt and Power Management Register Mnemonics Mnemonic or Portion Thereof Description Ethernet module transmit data interrupt Ethernet module receive data interrupt ENTC Ethernet module non-time-critical interrupt QSPI Queued serial peripheral interface IPL2, IPL1, IPL0 Interrupt priority level bits 2–0 Pending interrupt Power down enable Wakeup enable...
Page 177: Interrupt Control Register 2 (Icr2)
Interrupt Controller Registers Table 7-3. ICR Field Descriptions Bits Name Description 31, 27, Pending interrupt. Writing a 1 enables the value for the corresponding IPL ﬁeld to be set. Note: 23, 19, for external interrupts only, writing a one to this bit clears the corresponding interrupt latch. 15, 11, The external interrupt must be toggled before another interrupt is latched.
Page 178: Interrupt Control Register 4 (Icr4)
Interrupt Controller Registers Field USB4PI USB41IPL USB5PI USB5IPL USB6PI USB6IPL USB7PI USB7IPL Reset 0000_0000_0000_0000 Field DMAPI DMAIPL ERXPI ERXIPL ETXPI ETXIPL ENTCPI ENTCIPL Reset 0000_0000_0000_0000 Addr MBAR + 0x028 Figure 7-4. Interrupt Control Register 3 (ICR3) Table 7-3 describes ICR3 ﬁelds. 7.2.2.4 Interrupt Control Register 4 (ICR4) ICR4, Figure 7-5, is used to conﬁgure interrupts from various on-chip sources.
Page 179: Programmable Interrupt Transition Register (Pitr)
Interrupt Controller Registers Field INT1 INT2 INT3 INT4 TMR1 TMR2 TMR3 TMR4 Reset XXXX_1111 Read only Field UART1 UART2 PLI_P PLI_A USB0 USB1 USB2 USB3 Reset 1111_1111 Read only Field USB4 USB5 USB6 USB7 ENTC Reset 1111_1111 Read only Field QSPI INT5 INT6...
Page 180: Programmable Interrupt Wakeup Register (Piwr)
Interrupt Controller Registers Field INT1 INT2 INT3 INT4 — Reset 0000_0000_0000_0000 Field — INT5 INT6 — Reset 0000_0000_0000_0000 Addr MBAR + 0x034 Figure 7-7. Programmable Interrupt Transition Register (PITR) Table 7-5 describes PITR ﬁelds. Table 7-5. PITR Field Descriptions Bits Name Description 31–28,...
Page 181: Programmable Interrupt Vector Register (Pivr)
Interrupt Controller Registers Field INT1 INT2 INT3 INT4 TMR1 TMR2 TMR3 TMR4 Reset 1111_1111 Field UART1 UART2 PLI_P PLI_A USB0 USB1 USB2 USB3 Reset 1111_1111 Field USB4 USB5 USB6 USB7 ENTC Reset 1111_1111 Field QSPI INT5 INT6 SWTO — Reset 1111_0000 Address MBAR+0x038...
Page 182 Interrupt Controller Registers If the core initiates an interrupt acknowledge cycle prior to the PIVR being programmed, the interrupt controller returns the uninitialized interrupt vector (0x0F). If the core initiates an interrupt acknowledge cycle after the PIVR has been initialized, but there is no interrupt pending, the interrupt controller returns the user a spurious interrupt vector (0xxxx0_0000).
Page 183 Interrupt Controller Registers Table 7-8. MCF5272 Interrupt Vector Table Vector Number Bits 4–0 Source Function 01100 PLIA PLIC Asynchronous 01101 USB0 USB Endpoint 0 01110 USB1 USB Endpoint 1 01111 USB2 USB Endpoint 2 10000 USB3 USB Endpoint 3 10001 USB4 USB Endpoint 4 10010...
Page 184 Interrupt Controller Registers 7-12 MCF5272 User’s Manual...
Page 185: Overview
Chapter 8 Chip Select Module This chapter describes the chip select module, including the chip select registers, the conﬁguration and behavior of the chip select signals, and the global chip select functions. 8.1 Overview The chip select module provides user-programmable control of the eight chip select and four byte strobe outputs.
Page 186: Boot Cs0 Operation
Chip Select Registers NOTE: A detailed description of each bus access type supported by the MCF5272 device is given in Chapter 20, “Bus Operation.” 8.1.3 Boot CS0 Operation CS0 is enabled after reset and is used to access boot ROM. The memory port width of CS0 is deﬁned by the state of QSPI_CLK/BUSW1 and QSPI_CS0/BUSW0.
Page 187: Chip Select Base Registers (Csbr0–Csbr7)
Chip Select Registers 8.2.1 Chip Select Base Registers (CSBR0–CSBR7) The CSBRs, Figure 8-1, provide a model internal bus cycle against which to match actual bus cycles to determine whether a speciﬁc chip select should assert. A bus cycle in a speciﬁc chip select register causes the assertion of the corresponding external chip select.
Page 188 Chip Select Registers Table 8-2. CSBRn Field Descriptions (Continued) Bits Name Description 4–2 Transfer modiﬁer. Operates with TT to determine the access type. Function Reserved User data access User instruction access 011–100 Reserved Supervisor data access Supervisor instruction access Reserved 000–100 Reserved Emulator mode data access...
Page 189: Chip Select Option Registers (Csor0–Csor7)
Chip Select Registers Table 8-4. Chip Select Memory Address Decoding Priority Priority Chip Select Highest Chip select 0 Chip select 1 Chip select 2 Chip select 3 Chip select 4 Chip select 5 Chip select 6 Lowest Chip select 7 8.2.2 Chip Select Option Registers (CSOR0–CSOR7) CSOR0–CSOR7, Figure 8-2, are used to conﬁgure the address mask, additional setup/hold, extended burst capability, wait states, and read/write access.
Page 190 Chip Select Registers Table 8-5. CSORn Field Descriptions (Continued) Name Name Description RDAH Controls the address and attribute hold time after the termination, internal or external with TA, of a read cycle that hits in the chip select address space. 0 Do not hold address and attribute signals an extra cycle after chip select negates on reads.
Page 191: Overview
Chapter 9 SDRAM Controller This chapter describes conﬁguration and operation of the synchronous DRAM controller component of the SIM including a general description of signals involved in SDRAM operations. It provides interface information for memory conﬁgurations using most common SDRAM devices for both 16- and 32-bit wide data buses. The chapter concludes with signal timing diagrams.
Page 192 SDRAM Controller Signals bank selects are dedicated SDRAM signals. Figure 9-1 shows the SDRAM controller signal conﬁguration. SDRAM Controller SDRAMCS/CS7 RAS0 CAS0 SDWE BS[3:0] SDBA[1:0] SDCLKE SDCLK A10_PRECHG Address Multiplexer A[22:15] Internal 32-Bit Address Bus A[11:2]/SDA[9:0] A[14:13/SDA[12:11] Dynamic Bus Sizer D[31:0] Figure 9-1.
Page 193 SDRAM Controller Signals Table 9-1. SDRAM Controller Signal Descriptions Signal Description SDBA[1:0] SDRAM controller bank address select outputs. Assigned to internal high-order address signals by programming SDCR[BALOC]. This allows using SDRAM devices of different sizes without changing the board layout. See Table 9-7. SDCLK SDRAM (bus) clock (same frequency as CPU clock).
Page 194 SDRAM Controller Signals 64 Mbit 128 Mbit 256 Mbit DQ15 DQ15 DQ15 DQ14 DQ14 DQ14 DQ13 DQ13 DQ13 DQ12 DQ12 DQ12 DQ11 DQ11 DQ11 DQ10 DQ10 DQ10 DQML DQML DQML DQMH DQMH DQMH Figure 9-2. 54-Pin TSOP SDRAM Pin Definition Table 9-2 shows how BS[3:0] should be connected to DQMx for 16- and 32-bit SDRAM conﬁgurations.
Page 195: Interface To Sdram Devices
Interface to SDRAM Devices 9.3 Interface to SDRAM Devices The following tables describes possible memory conﬁgurations using most common SDRAM devices for 16- and 32-bit wide data buses. Table 9-3. Configurations for 16-Bit Data Bus 8-Bit 16-Bit Parameter 16 Mbyte 64 Mbyte 16 Mbyte 64 Mbyte...
Page 196: Sdram Banks, Page Hits, And Page Misses
SDRAM Banks, Page Hits, and Page Misses Table 9-5. Internal Address Multiplexing (16-Bit Data Bus) 8-Bit 16-Bit SDRAM Device Pin 16 Mbytes 64 Mbytes 16 Mbytes 64 Mbytes 128 Mbytes 256 Mbytes A8/A17 A8/A17 A8/A16 A8/A16 A8/A17 A8/A17 A9/A18 A9/A18 A9/A18 A9/A18 A10_PRECHG...
Page 197: Sdram Registers
SDRAM Registers of an activated page. Each bank can have one open page. A device with two banks can have two open pages. A device with four banks can have four open pages. The lower addresses of the row address are compared against the page address register content.
Page 198 SDRAM Registers Table 9-7. SDCR Field Descriptions Bits Name Description — Reserved, should be cleared. 14–13 MCAS Maximum CAS address. Determines which device address output carries the column address msb. For example, if the SDRAM device has eight column addresses and the data bus is conﬁgured for 32 bits, the column address appears on A[9:2], so the maximum column address is A9.
Page 199: Sdram Timing Register (Sdtr)
SDRAM Registers 9.5.2 SDRAM Timing Register (SDTR) The SDTR is used to conﬁgure SDRAM controller refresh counters for the type of SDRAM devices used and the number of clocks required for each type of SDRAM access. The reset value is 0x2115. For lower CPU clock frequencies, precharge and activate times can be reduced to eliminate up to 2 clock cycles from the read and write accesses.
Page 200: Auto Initialization
Auto Initialization Table 9-8. SDTR Field Descriptions (Continued) Bits Name Description 3–2 RAS-to-CAS delay. The reset value is 1, requiring 2 clock cycles for SDRAM activation. 00 1 cycle 01 2 cycles (default) 10 3 cycles 11 4 cycles 1–0 CAS latency.
Page 201: Performance
Performance After power-down completes, SDCR[SLEEP] is set, the SDRAM clock output is driven high, and SDCLKE is driven low. To wake up the SDRAMs, SDCR[GSL] must be cleared. SDCR[SLEEP] remains set while the SDRAM is exiting sleep mode and is cleared when the SDRAM completes the correct sequence to exit sleep mode.
Page 202 Performance Table 9-10. SDRAM Controller Performance, 32–Bit Port, (RCD = 0, RP = 0) (Contin- Number of System Clock Cycles SDRAM Access REG = 0, INV = 0 REG = 0, INV = 0 Single-beat write Page miss Page hit Burst read Page miss 7-1-1-1 = 10...
Page 203: Solving Timing Issues With Sdcr[Inv]
Solving Timing Issues with SDCR[INV] Table 9-12. SDRAM Controller Performance, 16-Bit Port, (RCD=0, RP=1) or (RCD=1, RP = 0) (Continued) Number of System Clock Cycles SDRAM Access REG = 0, INV = 0 REG = 1, INV = 0 Single-beat longword read Page miss 8-1 Page hit Single-beat write...
Page 204 Solving Timing Issues with SDCR[INV] capacitive loads on SDCLK can cause long delays on SDCLK, possibly causing SDRAM hold-time violations during writes. The clock may arrive at the same time as the write data. The write data setup time to SDCLK edge may not meet device requirements at the SDRAM.
Page 205 Solving Timing Issues with SDCR[INV] If the delay between shifted SDCLK and following internal system clock edge is shorter than the read access time of the SDRAM, data is sampled with the true CAS latency. CASL = 2 Internal SDCLK Data SDRAM read access time Delay SDCLK to CLK...
Page 206: Sdram Interface
SDRAM Interface programs the CAS latency of 2 and transfers it into the SDRAM mode register. After SDRAM initialization is conﬁrmed, initialization software should change SDTR[CLT] to CAS latency 1 but should not reinitialize the SDRAM. The SDRAM controller state machine now runs with CAS latency 1 and SDRAMs run with CAS latency 2, which increases bandwidth on the SDRAM bank and improves performance.
Page 207: Sdram Read Accesses
SDRAM Interface • 16-byte read or write bursts during Ethernet DMA transfers to/from SDRAM with access times of n-1-1-1 or n-1-1-1-1-1-1-1 depending on 32 or 16 bit SDRAM port width as described in the previous two paragraphs. These SDRAM accesses are shown in Figure 9-9 through Figure 9-15. The SDRAM supports a low-power, self-refreshing sleep mode as shown in Figure 9-14 and Figure 9-15.
Page 208 SDRAM Interface SDCLK Precharge Read CF2 Core Read Page Issue Old Page Activate Read Read Hit or Address New Page Miss? SDCLKE SDADR[13:0] 10_PRECHG SDBA[1:0] Bank x Bank y Bank y CASL = 2 Data Data Data Data D[31:0] SDCS RAS0 CAS0 SDWE...
Page 209: Sdram Write Accesses
SDRAM Interface SDCLK CF2 Core Read Read Page Issue Hit or Read Read Address Miss? SDCLKE SDADR[13:0] A10_PRECHG SDBA[1:0] Bank SDCS RAS0 CAS0 SDWE BS[3:0] Data Data Data Data D[31:0] Figure 9-10. SDRAM Burst Read, 32-Bit Port, Page Hit, Access = 5-1-1-1 9.10.2 SDRAM Write Accesses Like the read operations, shown in Figure 9-9 and Figure 9-10, the write operations require one cycle to issue the address (T1) and another (T2) to determine whether the access is page...
Page 210 SDRAM Interface SDCLK Precharge CF2 Core Write Write Page Issue Old Page Activate Hit or Write Write Address New Page Miss? SDCLKE SDADR[13:0] A10_PRECHG SDBA[1:0] Bank x Bank y Bank y SDCS RAS0 CAS0 SDWE BS[3:0] Data Data Data Data D[31:0] Figure 9-11.
Page 211: Sdram Refresh Timing
SDRAM Interface SDCLK CF2 Core Write Write Page Issue Hit or Write Write Address Miss? SDCLKE SDADR[13:0] A10_PRECHG SDBA[1:0] Bank SDCS RAS0 CAS0 SDWE BS[3:0] Data Data Data Data D[31:0] Figure 9-12. SDRAM Burst Write, 32-Bit Port, Page Hit, Access = 3-1-1-1 9.10.3 SDRAM Refresh Timing Figure 9-13 shows refresh-cycle timing.
Page 212 SDRAM Interface SDCLK Next Command Precharge Auto All Banks Refresh SDCLKE SDADR[13:0] A10_PRECHG SDBA[1:0] SDCS RAS0 CAS0 SDWE Figure 9-13. SDRAM Refresh Cycle Figure 9-14 shows the timing for entering SDRAM self-refresh mode. During a command (T1), the SDRAM writes all of its on-chip RAM page buffers PRECHARGE ALL back into the SDRAM array.
Page 213 SDRAM Interface Internal Clock SDCLK Precharge Self All Banks NOP Refresh SDCR[SLEEP] SDCLKE SDADR[13:0] A10_PRECHG SDBA[1:0] SDCS RAS0 CAS0 SDWE Figure 9-14. Enter SDRAM Self-Refresh Mode Figure 9-15 shows the timing for exiting SDRAM self-refresh mode. Note that SDCR[GSL] is sampled on the rising edge of the internal clock. If it is 0, as it is here, SDRAM controller signals become active on the following negative clock edge.
Page 214 SDRAM Interface Internal Clock SDCLK SDCR[GSL] SDCR[SLEEP] SDCLKE SDADR[13:0] A10_PRECHG SDBA[1:0] SDCS RAS0 CAS0 SDWE Figure 9-15. Exit SDRAM Self-Refresh Mode 9-24 MCF5272 User’s Manual...
Page 215: Dma Data Transfer Types
Chapter 10 DMA Controller The MCF5272 has a one-channel DMA controller that supports memory-to-memory DMA transfers that can be used for block data moves. This chapter describes in detail its signals, registers, and operating modes. 10.1 DMA Data Transfer Types A source and destination address must be speciﬁed for any dual-address DMA transfer.
Page 216: Dma Address Modes
DMA Address Modes 10.2 DMA Address Modes The DMA address mode determines how the address output by the channel is updated after a transfer to be ready for the next transfer. The two following modes are supported: • Static address mode—The address remains unchanged after the transfer completes. This mode should be used when the source or destination address is the FIFO data port of an on-chip peripheral.
Page 217 DMA Controller Registers Table 10-2. DMR Field Descriptions Bits Name Description RESET Reset. Writing a 1 to this location causes the DMA controller to reset to a condition where no transfers are taking place. EN is cleared, preventing new transfers. Enable.
Page 218: Dma Interrupt Register (Dir)
DMA Controller Registers Table 10-2. DMR Field Descriptions (Continued) Bits Name Description 4–2 SRCT Source addressing type. Used internal to the MCF5272 to qualify the address bits. The value should be compatible with the CSCRn[TM] value used for external RAM or peripheral device access.
Page 219: Dma Source Address Register (Dsar)
DMA Controller Registers Table 10-3. DIR Field Descriptions (Continued) Bits Name Description ASCEN Address sequence complete interrupt enable. 0 ASC interrupt is disabled. 1 ASC interrupt is enabled. — Reserved, should be cleared. TEEN Transfer error interrupt enable. 0 TE interrupt is disabled. 1 TE interrupt is enabled.
Page 220: Dma Destination Address Register (Ddar)
DMA Controller Registers Field SRCADR Reset 0000_0000_0000_0000_0000_0000_0000_0000 Addr MBAR + 0x00EC Figure 10-3. DMA Source Address Register (DSAR) 10.3.4 DMA Destination Address Register (DDAR) The DDAR provides a 32-bit address that the DMA controller drives onto the internal address bus for all of the channel’s write accesses. The address is altered after each write access according to the addressing mode.
Page 221: Overview
Chapter 11 Ethernet Module This chapter begins with a feature-set overview, a functional block diagram, and transceiver connection information for both MII and seven-wire serial interfaces. The chapter concludes with detailed descriptions of operation and the programming model. 11.1 Overview The MCF5272’s integrated fast Ethernet media access controller (MAC) performs the full set of IEEE 802.3/Ethernet CSMA/CD media access control and channel interface functions.
Page 222: Module Operation
Module Operation 11.2 Module Operation The FEC is implemented using a combination of hardware and microcode. Figure 11-1 shows a functional block diagram of this module. Figure 11-1. Ethernet Block Diagram Figure 11-2 shows a fast Ethernet module. Internal Bus Interface Dedicated DMA/ Descriptor Access FIFO...
Page 223: Transceiver Connection
Transceiver Connection The descriptor controller manages data ﬂow in both transmit and receive directions. It is programmed with microcode to open and close buffer descriptors, control the transmit collision recovery process, and ﬁlter received frame addresses. The descriptor controller accesses both the transmit and receive descriptor rings through the descriptor access block.
Page 224: Fec Frame Transmission
FEC Frame Transmission Table 11-2. Seven-Wire Mode Configuration (Continued) Signal Description MCF5272 Pin Receive enable E_RxDV Receive data E_RxD[0] Unused, conﬁgure as PB14 E_RxER Unused input, tie to ground E_CRS Unused, conﬁgure as PB[13:11] E_RxD[3:1] Unused output, ignore E_TxER Unused, conﬁgure as PB[10:8] E_TxD[3:1] Unused, conﬁgure as PB15 E_MDC...
Page 225: Fec Frame Reception
FEC Frame Transmission from system memory in case of a collision. This improves external bus use and reduces latency whenever the backoff process results in an immediate retransmission. See Figure 11-27 on page 11-36 for the following discussion. When the end of the last transmit buffer in the current frame is reached, the 32-bit frame check sum is appended (if TxBD[TC] is set) and transmission is disabled (E_TxEN is negated).
Page 226: Cam Interface
In addition to the FEC address recognition logic, an external CAM may be used for frame reject with no additional pins other than those in the MII interface. This CAM interface is documented in an application note titled “Using Motorola’s Fast Static RAM CAMs with the MPC860T’s Media Independent Interface,” located at the following URL: http://www.mot.com/SPS/RISC/netcomm/aesop/mpc8XX/860/860tcam.pdf.
Page 227: Ethernet Address Recognition
FEC Frame Transmission 11.4.3 Ethernet Address Recognition The FEC ﬁlters the received frames based on the type of destination media access controller address (hardware address). There are three destination address (DA) types: • Individual (unicast) • Group (multicast) • Broadcast (all-ones group address). The difference between an individual address and a group address is determined by the I/G bit in the destination address ﬁeld.
Page 228: Hash Table Algorithm
FEC Frame Transmission Check Address I/G Address Broadcast True Address False Receive Frame True Hash Match False Receive Frame False True Perfect Match Receive Frame True (R_CNTRL[PROM] = 1) Promiscuous Mode False Receive Frame (R_CNTRL[PROM] = 0) Set Miss Bit Discard Frame Figure 11-4.
Page 229: Interpacket Gap Time
FEC Frame Transmission The effectiveness of the hash table declines as the number of addresses increases. The hash table registers must be initialized by the user. The CRC32 polynomial to use in computing the hash is as follows: 11.4.5 Interpacket Gap Time The minimum interpacket gap time for back-to-back transmission is 96 bit times.
Page 230: Ethernet Error-Handling Procedure
FEC Frame Transmission 11.4.8 Ethernet Error-Handling Procedure The FEC reports frame reception and transmission error conditions through the buffer descriptors and the I_EVENT register. 11.4.8.1 Transmission Errors Transmission errors are deﬁned in Table 11-4. Table 11-4. Transmission Errors Error Description Transmitter The FEC sends 32 bits that ensure a CRC error and stops transmitting.
Page 231: Programming Model
Programming Model 11.5 Programming Model This section gives an overview of the registers, followed by a description of the buffers. The FEC is programmed by a combination of control/status registers (CSRs) and buffer descriptors. The CSRs are used for mode control and to extract global status information. The descriptors are used to pass data buffers and related buffer information between the hardware and software.
Page 232: Ethernet Control Register (Ecntrl)
Programming Model Table 11-6. FEC Register Memory Map (Continued) Offset Name Width Description 0xC14 X_DES_START Pointer to transmit descriptor ring (X_DES_START), [p. 11-29] 0xC18 R_BUFF_SIZE Maximum receive buffer size, [p. 11-30] 0xC40 - FIFO RAM space 0xDFF The following sections describe each register in detail. 11.5.1 Ethernet Control Register (ECNTRL) The ECNTRL register, Figure 11-5, is used to enable/disable the FEC.
Page 233: Interrupt Event Register (I_Event)
Programming Model Table 11-7. ECNTRL Field Descriptions (Continued) Bits Name Description ETHER_EN Ethernet enable. When this bit is set, the FEC is enabled, and reception and transmission is possible. When this bit is cleared, reception is immediately stopped and transmission is stopped after a bad CRC is appended to any frame currently being transmitted.
Page 234: Interrupt Mask Register (I_Mask)
Programming Model Table 11-8. I_EVENT Field Descriptions (Continued) Bits Name Description Receive frame interrupt. A frame has been received and the last corresponding buffer descriptor has been updated. Receive buffer interrupt. A receive buffer descriptor has been updated. MII interrupt. The MII has completed the data transfer requested. EBERR FEC bus error.
Page 235: Receive Descriptor Active Register (R_Des_Active)
Programming Model Field — Reset 0000_0000_0000_0000 Read Only Field — IVEC — Reset 0000_0000_0000_0000 Read Only Addr MBAR + 0x84C Figure 11-7. Interrupt Vector Status Register (IVEC) Table 11-10. IVEC Field Descriptions Name Description 31–4 — Reserved, should be cleared. 3–2 IVEC Interrupt vector.
Page 236: Transmit Descriptor Active Register (X_Des_Active)
Programming Model Field — R_DES_ACTIVE — Reset 0000_0000_0000_0000 Read/Write Field — Reset 0000_0000_0000_0000 Read/Write Addr MBAR + 0x850 Figure 11-8. R_DES_ACTIVE Register Table 11-11. describes the R_DES_ACTIVE ﬁelds. Table 11-11. R_DES_ACTIVE Register Field Descriptions Name Description 31–25 — Reserved, should be cleared. R_DES_ACTIVE Set when this register is written, regardless of the value written.
Page 237: Mii Management Frame Register (Mii_Data)
Programming Model Field — X_DES_ACTIVE — Reset 0000_0000_0000_0000 Read/Write Field — Reset 0000_0000_0000_0000 Read/Write Addr MBAR +0x854 Figure 11-9. X_DES_ACTIVE Register Table 11-12. describes the X_DES_ACTIVE ﬁelds. Table 11-12. X_DES_ACTIVE Field Descriptions Bits Name Description 31–25 — Reserved, should be cleared. X_DES_ACTIVE Set to one when this register is written, regardless of the value written.
Page 238 Programming Model Table 11-13. describes the MII_DATA ﬁelds. Table 11-13. MII_DATA Field Descriptions Bits Name Description 31–30 Start of frame delimiter. Must be programmed to 01 for a valid MII management frame 29–28 Operation code. This ﬁeld must be programmed to 10 (read) or 01(write) to generate a valid MII management frame.
Page 239: Mii Speed Control Register (Mii_Speed)
Programming Model 11.5.8 MII Speed Control Register (MII_SPEED) The MII_SPEED register, Figure 11-11, provides control of the MII clock (E_MDC pin) frequency, allows dropping the preamble on the MII management frame and provides observability (intended for manufacturing test) of an internal counter used in generating the E_MDC clock signal.
Page 240: Fifo Receive Bound Register (R_Bound)
Programming Model MII_SPEED as a function of system clock frequency. Table 11-15. Programming Examples for MII_SPEED Register System Clock Frequency [MII_SPEED] E_MDC frequency 25 MHz 2.08 MHz 33 MHz 2.06 MHz 50 MHz 2.5 MHz 66 MHz 2.36 MHz 11.5.9 FIFO Receive Bound Register (R_BOUND) R_BOUND is a read-only register used to determine the upper address boundary of the FIFO RAM.
Page 241: Transmit Fifo Watermark (X_Wmrk)
Programming Model receive FIFOs. The transmit FIFO uses addresses from X_FSTART to R_FSTART - 4. The receive FIFO uses addresses from R_FSTART to R_BOUND - 4. The value in this register must be added to MBAR + 0x800 to determine the absolute address. R_FSTART needs to be written only to change the default value.
Page 242: Fifo Transmit Start Register (X_Fstart)
Programming Model Field — Reset 0000_0000_0000_0000 Read/Write Field — X_WMRK Reset 0000_0000_0000_00 Read/Write Addr MBAR + 0x8E4 Figure 11-14. Transmit FIFO Watermark (X_WMRK) Table 11-18. describes the X_WMRK ﬁelds. Table 11-18. X_WMRK Field Descriptions Bits Name Description 31–2 — Reserved, should be cleared. 1–0 X_WMRK Transmit FIFO watermark.
Page 243: Receive Control Register (R_Cntrl)
Programming Model Field — Reset 0000_0000_0000_0000 Read/Write Field — X_FSTART — Reset 0000_0 0001_1000 Read/Write Addr MBAR + 0x8EC Figure 11-15. FIFO Transmit Start Register (X_FSTART) Table 11-19. describes the X_FSTART ﬁelds. Table 11-19. X_FSTART Field Descriptions Bits Name Description 31–11 —...
Page 244: Maximum Frame Length Register (Max_Frm_Len)
Programming Model Table 11-20. R_CNTRL Field Descriptions Bits Name Description 31–4 — Reserved, should be cleared. PROM Promiscuous mode. All frames are accepted regardless of address matching. MII_MODE MII mode enable. Selects the external interface mode. Setting this bit to one selects MII mode, setting this bit equal to zero selects seven-wire mode (used only for serial 10 Mbps).
Page 245: Transmit Control Register (X_Cntrl)
Programming Model Table 11-21. MAX_FRM_LEN Field Descriptions Bits Name Description BRDCAST Broadcast address received. Set if the current receive frame contained a destination address of all ones (the broadcast address). Cleared if the current receive frame does not correspond to a broadcast address. MULTCAST Multicast address received.
Page 246: Ram Perfect Match Address Low (Addr_Low)
Programming Model Table 11-22. X_CNTRL Field Descriptions (Continued) Bits Name Description Heartbeat control. If set, the heartbeat check is performed following end of transmission and the HB bit in the status register is set if the collision input does not assert within the heartbeat window.
Page 247: Hash Table High (Hash_Table_High)
Programming Model Figure 11-20. Field ADDR_HIGH Reset Undeﬁned Read/Write Field ADDR_HIGH Reset 0000_0000_0000_0000 Read/Write Addr MBAR + 0xC04 Figure 11-20. RAM Perfect Match Address High (ADDR_HIGH) Table 11-24. ADDR_HIGH Field Descriptions Bits Name Description 31–0 ADDR_HIGH Bytes 4 (bits 31–24) and 5 (bits 23–16) of the 6-byte address. 11.5.17 Hash Table High (HASH_TABLE_HIGH) The HASH_TABLE_HIGH register, Figure 11-21, contains the upper 32 bits of the 64-bit hash table used in the address recognition process for receive frames with a multicast...
Page 248: Hash Table Low (Hash_Table_Low)
Programming Model Table 11-25. HASH_TABLE_HIGH Field Descriptions Bits Name Description 31–0 HASH_HIGH The HASH_TABLE_HIGH register contains the upper 32 bits of the 64-bit hash table used in the address recognition process for receive frames with a multicast address. Bit 31 of HASH_TABLE_HIGH contains hash index bit 63. Bit 0 of HASH_TABLE_HIGH contains hash index bit 32.
Page 249: Pointer-To-Transmit Descriptor Ring (X_Des_Start)
Programming Model This register is not reset and must be initialized by the user prior to operation. Field R_DES_START Reset Undeﬁned Read/Write Field R_DES_START Reset Undeﬁned Read/Write Addr MBAR + 0xC10 Figure 11-23. Pointer to Receive Descriptor Ring (R_DES_START) Table 11-27. R_DES_START Field Descriptions Bits Name Description...
Page 250: Receive Buffer Size Register (R_Buff_Size)
Programming Model Table 11-28. X_DES_START Field Descriptions Bits Name Description 31–2 X_DES_START Pointer to start of transmit buffer descriptor queue. 1–0 — Reserved, should be cleared. 11.5.21 Receive Buffer Size Register (R_BUFF_SIZE) The R_BUFF_SIZE registers dictates the maximum size of all receive buffers. Note that because receive frames are truncated at 2k-1 bytes, only bits 10–4 are used.
Page 251: Hardware Initialization
Programming Model As soon as the FEC is initialized and enabled, it operates autonomously. Typically, the driver writes only to R_DES_ACTIVE, X_DES_ACTIVE, and I_EVENT during operation. 11.5.22.1 Hardware Initialization In the FEC, hardware resets only those registers that generate interrupts to the MCF5272 processor or cause conﬂict on bidirectional buses.
Page 252: Fec Initialization
Programming Model Table 11-32. User Initialization Process (before ETHER_EN) (Continued) Step Description Set IVEC (deﬁne ILEVEL) Set R_FSTART (optional) Set X_FSTART (optional) Set ADDR_HIGH and ADDR_LOW Set HASH_TABLE_HIGH and HASH_TABLE_LOW Set R_BUFF_SIZE Set R_DES_START Set X_DES_START Set R_CNTRL Set X_CNTRL Set MII_SPEED (optional) Initialize (Empty) TxBD Initialize (Empty) RxBD...
Page 253: Buffer Descriptors
Buffer Descriptors 11.6 Buffer Descriptors Data associated with the FEC controller is stored in buffers, which are referenced by buffer descriptors (BDs) organized as tables in the dual-port RAM. These tables have the same basic conﬁguration as those used by the USB. The BD table allows users to deﬁne separate buffers for transmission and reception.
Page 254: Ethernet Receive Buffer Descriptor (Rxbd)
Buffer Descriptors 11.6.1.1 Ethernet Receive Buffer Descriptor (RxBD) In the RxBD, the user initializes the E and W bits in the ﬁrst word and the pointer in the second word. When the buffer has been sent as a DMA, the FEC will modify the E, L, M, LG, NO, SH, CR, and OV bits and write the length of the used portion of the buffer in the ﬁrst word.
Page 255 Buffer Descriptors The ﬁrst word of the RxBD contains control and status bits. Its format is detailed below. Table 11-34. RxBD Field Descriptions Bits Name Description Empty. Written by the FEC (= 0) and user (= 1). 0 The data buffer associated with this BD has been ﬁlled with received data, or data reception has been aborted due to an error condition.
Page 256: Ethernet Transmit Buffer Descriptor
Buffer Descriptors Table 11-34. RxBD Field Descriptions (Continued) Bits Name Description Offset Data Written by the FEC. Data length is the number of octets written by the FEC into this BD’s Length data buffer if L = 0 (the value is equal to R_BUFF_SIZE), or the length of the frame including CRC if L = 1.
Page 257 Buffer Descriptors Table 11-35. TxBD Field Descriptions Bits Name Description Ready. Written by the FEC (= 0) and user (= 1). 0 The data buffer associated with this BD is not ready for transmission. The user is free to manipulate this BD or its associated data buffer. The FEC clears this bit after the buffer has been transmitted or after an error condition is encountered.
Page 258: Differences Between Mcf5272 Fec And Mpc860T Fec
Differences between MCF5272 FEC and MPC860T FEC Table 11-35. TxBD Field Descriptions (Continued) Bits Name Description Data Length Written by the user. Data length is the number of octets the FEC should transmit from this BD’s data buffer. It is never modiﬁed by the FEC. Bits [10–0] are used by the DMA engine;...
Page 259: Introduction
Chapter 12 Universal Serial Bus (USB) This chapter provides an overview of the USB module of the MCF5272, including detailed operation information and the USB programming model. Connection examples and circuit board layout considerations are also provided. The USB Speciﬁcation, Revision 1.1 is a recommended supplement to this chapter. It can be downloaded from http://www.usb.org.
Page 260 Introduction Peripheral Peripheral Peripheral Figure 12-1. The USB “tiered star” topology. The USB cables contain four wires, two for data and two for power. The USB full-speed bit rate is 12 Mbps. A limited-capability, low-speed mode is also deﬁned at 1.5 Mbps. The MCF5272 includes the following features: •...
Page 261: Module Operation
Module Operation • Supports remote wakeup • Detects start-of-frame and missed start-of-frame for isochronous endpoint synchronization • Notiﬁcation of start-of-frame, reset, suspend, and resume events 12.2 Module Operation The MCF5272 USB system consists of a protocol state machine which controls the transmitter and receiver modules.
Page 262: Usb Transceiver Interface
Module Operation 12.2.1.1 USB Transceiver Interface The USB module supports either an internal or external USB transceiver. USB_D+ and USB_D- drive USB cable D+ and D- lines, respectively. With additional external protection circuitry, equipment can be built that complies with Universal Serial Bus Speciﬁcation, Rev.
Page 263: Endpoint Controllers
Module Operation • For received data: — Sync detection — Packet identiﬁcation — End-of-packet detection — Serial-to-parallel conversion — CRC validation — NRZI decoding — Bit unstufﬁng • For error detection: — Bad CRC — Timeout waiting for end-of-packet — Bit stufﬁng violations 12.2.1.4 Endpoint Controllers The MCF5272 has eight independent endpoint controllers that manage data transfer between the on-chip CPU and the USB host for each endpoint.
Page 264 Module Operation Table 12-1. USB Device Requests Device Request USB Request Processor Action clear_feature Request processor clears the feature speciﬁed by the feature selector parameter. Currently, remote wakeup and endpoint halt are the only features deﬁned by the USB speciﬁcation. If the feature to be cleared is remote wakeup, the USB block disables the remote wakeup functionality.
Page 265: Register Description And Programming Model
Register Description and Programming Model 12.3 Register Description and Programming Model This section contains a detailed description of each register and its speciﬁc function. 12.3.1 USB Memory Map The operation of the USB is controlled by writing control bytes into the appropriate registers.
Page 266 Register Description and Programming Model Table 12-2. USB Memory Map (Continued) Offset [31:24] [23:16] [15:8] [7:0] 0x1068 Reserved USB Endpoint 7 Control Register (EP7CTL) 0x106C USB General/Endpoint 0 Interrupt Status Register (EP0ISR) 0x1070 Reserved USB Endpoint 1 Interrupt Status Register (EP1ISR) 0x1074 Reserved USB Endpoint 2 Interrupt Status Register (EP2ISR)
Page 267: Register Descriptions
Register Description and Programming Model 12.3.2 Register Descriptions The following are detailed register diagrams and ﬁeld descriptions. 12.3.2.1 USB Frame Number Register (FNR) Once every 1 ms, the USB host issues a start-of-frame packet containing a frame number. The FNR register captures this frame number.
Page 268: Usb Real-Time Frame Monitor Register (Rfmr)
Register Description and Programming Model Table 12-4. FNMR Field Descriptions Bits Name Description 15–11 — Reserved, should be cleared 10–0 FRM_MAT Frame number match value. Contains the USB frame number match value. When the FNR value equals the value in the register, a FRM_MAT interrupt is generated. 12.3.2.3 USB Real-Time Frame Monitor Register (RFMR) The value in the RFMR can be used to determine approximately how much time has elapsed since the USB host sent its last start-of-frame packet.
Page 269: Usb Function Address Register (Far)
Register Description and Programming Model Field — RTFM_MAT Reset 0000_0000_0000_0001 Addr MBAR + 0x100E Figure 12-6. USB Real-Time Frame Monitor Match Register (RFMMR) Table 12-6 lists ﬁeld descriptions for the USB real-time frame monitor match register. Table 12-6. RFMMR Field Descriptions BIts Name Description...
Page 270: Usb Device Request Data 1 And 2 Registers (Drr1/ 2)
Register Description and Programming Model Figure 12-8 shows the USB alternate settings register. The conﬁguration descriptors must be read by the user in order to determine which interfaces are currently valid. Field IF15_AS IF14_AS IF13_AS IF12_AS IF11_AS IF10_AS IF9_AS IF8_AS Reset 0000_0000_0000_0000 Read...
Page 271: Usb Specification Number Register (Specr)
Register Description and Programming Model Field wLength Reset 0000_0000_0000_0000 Read Field wIndex Reset 0000_0000_0000_0000 Read Addr MBAR + 0x101C Figure 12-10. USB Device Request Data 2 Register (DRR2) 12.3.2.8 USB Speciﬁcation Number Register (SPECR) Figure 12-11 shows the USB speciﬁcation number register. Field SPEC Reset...
Page 272 Register Description and Programming Model Field CONFIG WAKE_ST — HALT_ST DIR — Reset 0000_0000_0000_0001 Read Addr MBAR + 0x1026 Figure 12-12. USB Endpoint 0 Status Register (EP0SR) Table 12-10 lists ﬁeld descriptions the USB endpoint 0 status register. Table 12-10. EP0SR Field Descriptions Bits Name Descriptions...
Page 273: Usb Endpoint 0 In Configuration Register (Iep0Cfg)
Register Description and Programming Model Field MAX_PACKET — FIFO_SIZE Reset 0000_0000_0000_0000 Field FIFO_SIZE — FIFO_ADDR Reset 0000_0000_0000_0000 Addr MBAR + 0x1028 Figure 12-13. USB Endpoint 0 IN Configuration Register (IEP0CFG) Table 12-11 lists ﬁeld descriptions for the IEP0CFG register. Only longword writes are allowed.
Page 274: Usb Endpoint 0 Control Register (Ep0Ctl)
Register Description and Programming Model Field MAX_PACKET — FIFO_SIZE Reset 0000_0000_0000_0000 Field FIFO_SIZE — FIFO_ADDR Reset 0000_0000_0000_0000 Addr MBAR + 0x102C Figure 12-14. USB Endpoint 0 OUT Configuration Register See Table 12-11 for a description of the ﬁelds. 12.3.2.12 USB Endpoint 1–7 Conﬁguration Register (EPnCFG) Figure 12-15 shows the USB endpoint 1–7 conﬁguration register.
Page 275 Register Description and Programming Model Field — Reset 0100_0000 Field — DEBUG WOR_LVL WOR_EN Reset 0000_0000 Field CLK_SEL RESUME AFE_EN BUS_PWR USB_EN CFG_RAM_VAL CMD_ERR CMD_OVER Reset 0000_0000 Field CRC_ERR — OUT_LVL IN_LVL IN_DONE — Reset 0000_0000 Addr MBAR + 0x104C Figure 12-16.
Page 276 Register Description and Programming Model Table 12-12. EP0CTL Field Descriptions (Continued) Bits Name Description RESUME Generates RESUME condition. Used to exit the SUSPEND state. The USB control logic ensures the forced resume duration is greater than 10 ms. This command bit is write-only and always returns 0 when read.
Page 277: Usb Endpoint 1–7 Control Register (Epncfg)
Register Description and Programming Model Table 12-12. EP0CTL Field Descriptions (Continued) Bits Name Description CRC_ERR CRC error generation enable. This bit enables CRC error generation for debug and test purpose. In order to use this feature, the DEBUG bit must be set. Enabling this bit causes a CRC error on the next data packet transmitted.
Page 278 Register Description and Programming Model Field — Reset 0000_0000 Field CRC_ERR ISO_MODE — FIFO_LVL IN_DONE STALL Reset 0000_0000 Addr MBAR + 0x1052, 0x1056, 0x105A, 0x105E, 0x1062, 0x1066, 0x106A Figure 12-17. USB Endpoint 1-7 Control Register (EP Table 12-13 lists the ﬁeld descriptions for the USB endpoint 1–7 control register. Table 12-13.
Page 279: Usb Endpoint 0 Interrupt Mask (E0Pimr) And General/Endpoint 0 Interrupt Registers (Ep0Isr)
Register Description and Programming Model Table 12-13. EP CR Field Descriptions Bits Name Description IN_DONE This bit controls the USB's response to IN tokens from the host. Set at Reset and on an EOT event and must be cleared by software when the last byte of a transfer has been written to the IN-FIFO.
Page 280 Register Description and Programming Model Field — Reset 0000_0000 Field — DEV_CFG Reset 0000_0000 Field VEND_REQ FRM_MAT ASOF WAKE_CHG RESUME SUSPEND RESET Reset 0000_0000 Field OUT_EOT OUT_EOP OUT_LVL IN_EOT IN_EOP UNHALT HALT IN_LVL Reset 0000_0000 Addr MBAR + 0x108C (E0IMR); MBAR + 0x106C (G/E0IR) Figure 12-18.
Page 281 Register Description and Programming Model Table 12-14. EP0IMR and EP0ISR Field Descriptions (Continued) Bits Name Description VEND_REQ Class or vendor speciﬁc request received. Set when a class- or vendor-speciﬁc request is received. When the application detects assertion of VEND_REQ interrupt, it should begin reading DRR1 and DRR2.
Page 282: Usb Endpoints 1–7 Status / Interrupt Registers (Epnisr)
Register Description and Programming Model Table 12-14. EP0IMR and EP0ISR Field Descriptions (Continued) Bits Name Description IN_EOT End of transfer. This bit is set when the end of a transfer has been reached for an IN endpoint. An EOT interrupt is generated when a packet with a size less than the maximum packet size or the ﬁrst zero-length packet following maximum size packets is sent.
Page 283: Usb Endpoint 1–7 Interrupt Mask Registers (Epnimr)
Register Description and Programming Model Table 12-15 lists ﬁeld descriptions for the USB endpoints 1–7 interrupt status registers. Table 12-15. EP ISR Field Descriptions Bits Name Description HALT_ST Current status of endpoint n. This bit indicates whether endpoint n is currently halted or active.
Page 284: Usb Endpoint 0–7 Data Registers (Epndat)
Register Description and Programming Model Field — EOT_EN EOP_EN UNHALT_EN HALT_EN FIFO_LVL_EN Reset 0000_0000_0000_0000 Addr MBAR + 0x1092, 0x1096, 0x109A, 0x109E, 0x10A2, 0x10A6, 0x10AA Figure 12-20. USB Endpoint 1-7 Interrupt Mask Registers (EP IMR) Table 3-16 lists ﬁeld descriptions for the USB endpoint 1–7 interrupt mask register. Table 12-16.
Page 285: Usb Endpoint 0–7 Data Present Registers (Epndpr)
Register Description and Programming Model 12.3.2.19 USB Endpoint 0–7 Data Present Registers (EPnDPR) Figure 12-23 shows the USB endpoint 0-7 data present registers. used to coordinate user access to FIFO with external devices to prevent data loss (overwrite) says how much free space is still available.
Page 286 Register Description and Programming Model words and longwords. The user must make sure that any word or longword ﬁelds are stored in the correct byte order. A device may support multiple conﬁgurations. Within any one conﬁguration, the device may support multiple interfaces. An interface consists of a set of endpoints that presents to the host a single feature or function of the device.
Page 287: Usb Module Access Times
Register Description and Programming Model 6. Interface #1 Descriptor 7. Endpoint #3 Descriptor 8. Conﬁguration #2 Descriptor 9. Interface #0 Descriptor 10. Endpoint #1 Descriptor 11. Conﬁguration #3 Descriptor 12. Interface #0 Descriptor 13. Endpoint #1 Descriptor 14. Endpoint #2 Descriptor 12.3.4 USB Module Access Times The access times for the USB module depend on whether the access is to a register, to an endpoint FIFO (EPnDAT register), or to the conﬁguration RAM.
Page 288: Software Architecture And Application Notes
Software Architecture and Application Notes 12.4 Software Architecture and Application Notes This section describes architecture and applications. 12.4.1 USB Module Initialization At power-up, the USB module should be initialized within 20 ms if the USB port is connected. This time corresponds to the 10 ms reset signaling and 10 ms reset recovery time when a device is detected.
Page 289: Data Flow
Software Architecture and Application Notes number, alternate setting for each interface, and each endpoint’s type and packet size. The USB module contains two separate 512-byte FIFO spaces: one for IN and one for OUT endpoints. The following guidelines must be adhered to when conﬁguring the FIFO’s: •...
Page 290: Control, Bulk, And Interrupt Endpoints
Software Architecture and Application Notes 12.4.4.1 Control, Bulk, and Interrupt Endpoints The data ﬂow for control, bulk, and interrupt endpoints can be handled the same way for all 3 types of endpoints. Control, bulk, and interrupt endpoints all support guaranteed data delivery.
Page 291: Isochronous Endpoints
Software Architecture and Application Notes 12.4.4.2 Isochronous Endpoints The data ﬂow for isochronous endpoints must be handled differently than the data ﬂow for non-isochronous endpoints. Data on isochronous endpoints is generally streaming data. Therefore, there is no concept of transfers and EOT. In addition, isochronous endpoints differ from other endpoint types in two distinct ways.
Page 292 Software Architecture and Application Notes 5. Repeat steps 2–4 until entire packet is received. 6. Wait for EOP or SOF interrupt and read any remaining data in the FIFO. 7. An EOT interrupt indicates a short or zero-length packet. 12.4.5 Class- and Vendor-Speciﬁc Request Operation The class- and vendor-speciﬁc requests are speciﬁc to a particular device class or vendor, and are not processed by the USB request processor.
Page 293: Endpoint Halt Feature
Line Interface 12.4.7 Endpoint Halt Feature USB has the ability to halt endpoints due to errors. The user is notiﬁed when an endpoint is halted and when the halt is cleared. When an endpoint is halted, the user should abort the current transfer and reinitialize the FIFO for the endpoint.
Page 294: Pcb Layout Recommendations
Line Interface to control the attach/detach detection by software instead of only at power on and off. With software control of the pull-up resistor, the user has unlimited time to initialize the USB module. The software controlled pull-up resistor can be implemented with only a few discrete components.
Page 295: Introduction
Chapter 13 Physical Layer Interface Controller (PLIC) This chapter provides detailed information about the MCF5272’s physical layer interface controller (PLIC), a module intended to support ISDN applications. The chapter begins with a description of operation and a series of related block diagrams starting with a high-level overview.
Page 296 Introduction through set 1. port 3 can use either pin set 1 or 3. Pin set 3 consists of data in and data out. Data clock and frame sync are common to pin set 1 and 3. In the case of set 1, which connects multiple ports, separate delayed frame sync generators are provided for each port which distinguish each port’s active time slots.
Page 297: Gci/Idl Block
GCI/IDL Block • Port 2: Connects through pin set 1. Operates as a slave-only port. Port 2 shares a data clock with port 1: DCL1 when port 1 is in slave mode or GDCL when port 1 is in master mode. A delayed frame sync, DFSC2, derived from FSC1, is connected to the DFSC2 output and fed to the port 2 IDL/GCI block.
Page 298: Gci/Idl B- And D-Channel Receive Data Registers
GCI/IDL Block 13.2.1 GCI/IDL B- and D-Channel Receive Data Registers B2 Shift Register B1 Shift Register D Shift Register Demultiplexing B1 Channel B2 Channel D Channel Circuitry Internal Bus Figure 13-2. GCI/IDL Receive Data Flow The maximum data rate received for each GCI/IDL port is 144 Kbps: the sum of two 64-Kbps B channels and one 16-Kbps D-channel.
Page 299: Gci/Idl B- And D-Channel Transmit Data Registers
GCI/IDL Block The CPU should service the B1 and B2 registers once every 500 µS. Overrun conditions can be avoided only if the CPU services these registers in a timely manner. The MCF5272 has 4 GCI/IDL interfaces. Thus the theoretical maximum is twelve 32-bit data registers to be read.
Page 300: Gci/Idl B- And D-Channel Bit Alignment
GCI/IDL Block Because the reception and transmission of information on the GCI/IDL interface is deterministic, a common interrupt is generated at the 2-KHz rate. It is expected that a common interrupt service routine services the transmit and receive registers. After reset, the B- and D-channel shift registers and shadow registers are initialized to all ones.
Page 301: B-Channel Hdlc Encoded Data
GCI/IDL Block (P3B2TR–P0B2TR),” for more information about some of these registers. Unencoded Din/Dout HDLC Encoded Din/Dout Frame 0 Frame 1 32-bit B1/B2 Receive/Transmit Registers, PnB1RR, PnB2RR, PnB1TR, PnB2TR Frame 0 Frame 1 Frame 2 Frame 3 Figure 13-6. B-Channel Unencoded and HDLC Encoded Data 13.2.3.2 B-Channel HDLC Encoded Data When the incoming B channels contain HDLC encoded data they are presented on the physical line least signiﬁcant bit (lsb) ﬁrst.
Page 302: D-Channel Unencoded Data
GCI/IDL Block position of a byte, with the last bit received aligned in the msb position. Because the presentation of HDLC encoded data on the physical interface is lsb ﬁrst, the lsb is right-aligned in the transmit and receive shift register. A D-channel byte is formed by concatenating two D bits from each of four frames.
Page 303: Gci/Idl D-Channel Contention
PLIC ports do not support any other form of D-channel contention such as the indirect mode found on the Motorola MC145574. In GCI mode, the DGRANT pin function found in IDL mode is disabled and the pin can be deﬁned for other functions. Please note...
Page 304: Automatic Echo Mode
GCI/IDL Block local-loopback mode, the information transmitted on the Dout pin is echoed back on Din during the same time slot. The PLIC transmitter and receiver should both be disabled when switching between modes. 13.2.4.1 Automatic Echo Mode The port automatically retransmits the received data on a bit-by-bit basis in this mode. The local CPU-to-receiver communication continues normally, but the CPU-to-transmitter link is disabled.
Page 305: Gci/Idl Interrupts
GCI/IDL Block 13.2.5 GCI/IDL Interrupts The PLIC module generates two interrupts—the periodic frame interrupt and the aperiodic status interrupt. 13.2.5.1 GCI/IDL Periodic Frame Interrupt The frame interrupt is a periodic 2-KHz interrupt as shown in Figure 13-10. This is the normal interrupt rate for servicing the incoming and outgoing B and D channels.
Page 306: Interrupt Control
PLIC Timing Generator interrupt. Once read, the interrupt is cleared. Each port and individual interrupts within each port is maskable. The following conditions for each of the ports can trigger this interrupt: • Monitor channel receive: ASR deﬁnes which port or ports have generated a monitor channel receive interrupt.
Page 307: Super Frame Sync Generation
PLIC Timing Generator Therefore, given a CLKIN of 66 MHz, the maximum frequency which can be synthesized with acceptable jitter is approximately 3.3 MHz. The clock generator uses a 14-bit counter to divide CLKIN. This limits the reference clock’s minimum frequency to CLKIN divided by 16,384. To summarize these two points: •...
Page 308: Frame Sync Synthesis
PLIC Timing Generator FSC0 2-KHz to CPU SFSC Gen FSC1 P0CR[M2-M0] P1CR[SFSM] P0SDR[15:0] DFSC0 DCL0/URT1_CLK Prog Delay 0 Mux 0 PA8/FSC0/FSR0 P1SDR[15:0] Port 0 DCL0 GCI/IDL DFSC0 DFSC1 Prog Delay 1 DCL1/GDCL1_OUT Mux 1 DCL1 FSC1/FSR1/DFSC1 Port 1 FSC1 GCI/IDL P2SDR[15:0] P1CR[M/S] DFSC2...
Page 309: Plic Register Memory Map
PLIC Register Memory Map • P0SDR settings affect DFSC[0–3] • P1SDR settings affect DFSC[1–3] • P2SDR settings affect only DFSC2 • P3SDR settings affect only DFSC3 13.4 PLIC Register Memory Map Table 13-1 lists the PLIC registers with their offset address from MBAR and their default value on reset.
Page 310: Plic Registers
PLIC Registers Table 13-1. PLIC Module Memory Map (Continued) MBAR [31:24] [23:16] [15:8] [7:0] Offset 0x036C Port2 GCI monitor Tx (P2GMT) Port3 GCI monitor Tx (P3GMT) 0x0370 Reserved GCI monitor Tx status GCI monitor Tx abort Reserved (PGMTS) (PGMTA) 0x0374 Port0 GCI C/I Rx Port1 GCI C/I Rx Port2 GCI C/I Rx...
Page 311: B2 Data Receive Registers (P0B2Rr–P3B2Rr)
PLIC Registers Field Frame 0 Frame 1 Reset 1111_1111 1111_1111 Read Only Field Frame 2 Frame 3 Reset 1111_1111 1111_1111 Read Only Addr MBAR + 0x300 (P0B1RR); 0x304 (P1B1RR); 0x308 (P2B1RR); 0x30C (P3B1RR) Figure 13-13. B1 Receive Data Registers P0B1RR–P3B1RR 13.5.2 B2 Data Receive Registers (P0B2RR–P3B2RR) All bits in these registers are read only and are set on hardware or software reset.
Page 312: B1 Data Transmit Registers (P3B1Tr–P0B1Tr)
PLIC Registers ports on the MCF5272. P0DRR is the D-channel byte for port 0, P1DRR the D channel for port 1, and so on. Each of the four byte-addressable registers, P3DRR-P0DRR, are packed to form one 32-bit register, PLRD, located at MBAR + 0x320. P0DRR is located in the MSB of the PLRD register, P3DRR is located in the LSB of the PLRD register.
Page 313: B2 Data Transmit Registers (P3B2Tr–P0B2Tr)
PLIC Registers 13.5.5 B2 Data Transmit Registers (P3B2TR–P0B2TR) All bits in these registers are read/write and are set on hardware or software reset. The PLTB2 registers contain four frames of transmit data for port n of channel B2. (P0B2TR is the B2 channel transmit data for port 0, P1B2TR is B2 transmit for port 1, and so on.) The data are packed from LSB to MSB.
Page 314: Port Configuration Registers (P0Cr–P3Cr)
PLIC Registers Field P0DTR P1DTR Reset 1111_1111 1111_1111 Read/Write Field P2DTR P3DTR Reset 1111_1111 1111_1111 Read/Write Addr MBAR + 0x348 (P0DTR); 0x349 (P1DTR); 0x34A (P2DTR); 0x34B (P3DTR) Figure 13-18. D Transmit Data Registers P3DTR–P0DTR 13.5.7 Port Conﬁguration Registers (P0CR–P3CR) P0CR ON/OFF —...
Page 315: Loopback Control Register (Plcr)
PLIC Registers Table 13-2. P0CR–P3CR Field Descriptions (Continued) Bits Name Description Master/Slave. Deﬁnes the direction of the DCL1 and FSC1 pins. 0 DCL1 and FSC1 are inputs and are sourced from an external master. Note: This bit is relevant to port 1 only, as port 0 is always in slave mode.
Page 316: Interrupt Configuration Registers (P0Icr–P3Icr)
PLIC Registers Field Reset 0000_0000 Read/Write Addr MBAR + 0x38F Figure 13-20. Loopback Control Register (PLCR) Table 13-3. PLCR Field Description Bits Name Description Loopback mode control, port 3. 00 Normal 01 Auto-echo 10 Local Loopback 11 Remote Loopback Loopback mode control, port 2. See LM3. Loopback mode control, port 1.
Page 317 PLIC Registers Table 13-4. P0ICR–P3ICR Field Descriptions Bits Name Description Interrupt enable. Allows the port to generate interrupts to the CPU. When cleared, the IE bit masks all periodic and aperiodic interrupts associated with the respective port. 14–12 — Reserved, should be cleared. Interrupt enable for the C/I channel receive.
Page 318: Periodic Status Registers (P0Psr–P3Psr)
PLIC Registers 13.5.10 Periodic Status Registers (P0PSR–P3PSR) All bits in these registers are read only and are set on hardware or software reset. P0PSR–3 — DTUE B2TUE B1TUE DROE B2ROE B1ROE DTDE B2TDE B1TDE DRDF B2RDE B1RDF Reset 0000_0000_0000_0000 Read Only Addr MBAR + 0x384 (P0PSR);...
Page 319: Aperiodic Status Register (Pasr)
PLIC Registers Table 13-5. P0PSR–P3PSR Field Descriptions Bits Name Description B2TDE B2 data transmit data empty. This bit is set when the data in the PLTB2 transmit data register for the respective port has been transferred to the transmit shadow register. This bit is cleared when the CPU writes data to PLTB2.
Page 320: Gci Monitor Channel Receive Registers (P3Gmr–P0Gmr)
PLIC Registers Table 13-6. PASR Field Descriptions (Continued) Bits Name Description 13, 9, 5, 1 GMRn GCI monitor received. When set, this bit indicates that data has been written to a monitor channel receive register. An interrupt is queued when this bit is set if the GMR interrupt enable bit has been set in the corresponding PLICR register.
Page 321: Gci Monitor Channel Transmit Registers (P0Gmt–P3Gmt)
PLIC Registers Table 13-7. P0GMR–P3GMR Field Descriptions Bits Name Description Monitor change. 0 Default at reset. 1 Indicates to the CPU that the monitor channel data byte written to the respective PLGMR register has changed and that the data is available for processing. Automatically cleared by the CPU when the PLGMR register has been read.
Page 322: Gci Monitor Channel Transmit Abort Register (Pgmta)
PLIC Registers 13.5.14 GCI Monitor Channel Transmit Abort Register (PGMTA) All bits in this register are read/write and are cleared on hardware or software reset. The PGMTA register contains the abort control bits for each of the four ports on the MCF5272 for the transmit monitor channel.
Page 323: Gci C/I Channel Receive Registers (P0Gcir–P3Gcir)
PLIC Registers Table 13-10. PGMTS Field Descriptions Bits Name Description ACK3 Acknowledge, port 3. 0 Default reset value. 1 Indicates to the CPU that the GCI controller has transmitted the previous monitor channel information. Automatically cleared by the CPU reading the register. The clearing of this bit by reading this register also clears the aperiodic GMT interrupt.
Page 324 PLIC Registers Table 13-11. P0GCIR–P3GCIR Field Descriptions Bits Name Description 31–29, 23–21, — Reserved, should be cleared. 15–13, 7–5 28, 20, 12, 4 Full. This bit is set by the C/I channel controller to indicate to the CPU that new C/I channel data has been received and is available for processing.
Page 325: Gci C/I Channel Transmit Registers (P3Gcit–P0Gcit)
PLIC Registers 13.5.17 GCI C/I Channel Transmit Registers (P3GCIT–P0GCIT) All bits in these registers are read/write and are cleared on hardware or software reset. The PLGCIT registers are 8-bit registers containing the monitor channel bits to be transmitted for each of the four ports on the MCF5272. Field —...
Page 326: D-Channel Status Register (Pdcsr)
PLIC Registers Field — ACK3 ACK2 ACK1 ACK0 Reset 0000_0000 Read Only Addr MBAR + 0x37F Figure 13-30. GCI C/I Channel Transmit Status Register (PGCITSR) Table 13-13. PGCITSR Field Descriptions Bits Name Description 7–4 — Reserved, should be cleared. ACK3 Acknowledge, port 3.
Page 327: D-Channel Request Register (Pdrqr)
PLIC Registers Table 13-14. PDCSR Field Descriptions Bits Name Description D-channel grant, port 0. See DG1. D-channel change, port 3. 0 Default reset value. 1 Indicates that a value other than 0xFF (all ones) exists the D-channel receive register. D-channel change, port 2. See DC3. D-channel change, port 1.
Page 328: Sync Delay Registers (P0Sdr–P3Sdr)
PLIC Registers 13.5.21 Sync Delay Registers (P0SDR–P3SDR) All bits in these registers are read/write and are cleared on hardware or software reset. The PLSD registers contain the frame sync delay bits for each of the four ports on the MCF5272. Field FSW1 FSW0 —...
Page 329: Application Examples
Application Examples 15 14 Field NBP — FDIV CMULT Reset 0000_0000_0000_0000 Read/Write Addr MBAR + 0x39E Figure 13-34. Clock Select Register (PCSR) Table 13-17. PCSR Field Descriptions Bits Name Description Non-bypass mode select for the clock generation module. 0 The clock generation module is bypassed. Gen_FSC and GDCL are connected to FSC0 and DCL0.
Page 330: Plic Initialization
Application Examples 13.6.2 PLIC Initialization The ports on the PLIC module of the MCF5272 require a number of registers to be conﬁgured after power-on reset and prior to use. The following are the steps necessary for initializing the ports. The port conﬁguration register, PLCR, and the interrupt conﬁguration register, PLICR, must be initialized before using any port.
Page 331 Application Examples FSM (port 1 Only) GCI ACT (GCI ONLY) SCIT MODE (GCI ONLY) Reserved SLAVE MODE B2 msb First IDL10 MODE B1 msb First Reserved B2 Disabled Port on B1 Disabled 15 14 13 12 11 10 P1CR Figure 13-35. Port 1 PLCR Configuration The programming of the port 1 PLCR register in the above example is achieved with the following ColdFire code sequence assuming the equates and init sections include the following:...
Page 332: Example 1: Isdn Soho Pbx With Ports 0, 1, 2, And 3
Application Examples Reserved DTIE enabled B2TIE disabled B1TIE disabled GCI only DRIE enabled Port 0 only B2RIE disabled IE enabled B1RIE disabled 15 14 13 12 11 10 P1ICR Figure 13-36. Port 1 PLICR Configuration The programming of the port 1 PLICR in the above example is achieved with the following ColdFire code sequence assuming the equates and init sections as in the previous PLCR example: move.w...
Page 333 BCLKT Figure 13-37. ISDN SOHO PABX Example In the above example, Motorola’s MC14LC5480 CODECs and MC145574 S/T transceiver are shown. The S/T transceiver in this example is connected to port 0 and the FSC0 frame sync signal is used exclusively for synchronizing the data on the transceiver’s IDL interface.
Page 334 Application Examples is receiving and transmitting on the B1 or the B2 time slot. See the MC14LC5480 data sheet for further information. Figure 13-38 shows the IDL bus timing relationship of the CODECs and MC145574 transceiver when in standard IDL2 10-bit mode with a common frame sync. FSC0 FSC1 DFSC2...
Page 335: Example 2: Isdn Soho Pbx With Ports 1, 2, And 3
BCLKT Figure 13-39. ISDN SOHO PABX Example In the above example, Motorola’s MC14LC5480 CODECs and MC145572 U transceiver are shown. The U transceiver in this example is connected to port 1 and the FSC1 frame sync signal is used exclusively for synchronizing the data on the U transceiver’s IDL interface.
Page 336: Example 3: Two-Line Remote Access With Ports 0 And 1
Application Examples Figure 13-40 shows the IDL bus timing relationship of the CODECs and U transceiver when in standard IDL2 10-bit mode with a common frame sync. FSC1 DFSC2 DFSC3 Din1/ Dout1 U Transceiver CODEC 1 CODEC 2 CODEC 3 CODEC 4 Figure 13-40.
Page 337 IDL CLK Figure 13-41. Two-Line Remote Access Two of Motorola’s MC145574 S/T transceivers are shown connected to ports 0 and 1. The frame sync control signal FSC0 is connected to S/T transceiver one, while FSC1 is connected to transceiver two.
Page 338 Application Examples 13-44 MCF5272 User’s Manual...
Page 339: Queued Serial Peripheral Interface (Qspi) Module
Chapter 14 Queued Serial Peripheral Interface (QSPI) Module This chapter describes the queued serial peripheral interface (QSPI) module. Following a feature-set overview is a description of operation including details of the QSPI’s internal RAM organization. The chapter concludes with the programming model and a timing diagram.
Page 340: Interface And Pins
Module Description 14.3.1 Interface and Pins The module provides as many as 15 ports and a total of seven signals: QSPI_Dout, QSPI_Din, QSPI_CLK, QSPI_CS0, QSPI_CS1, QSPI_CS2, and QSPI_CS3. Peripheral chip-select signals, QSPI_CS[0:3], are used to select an external device as the source or destination for serial data transfer.
Page 341: Internal Bus Interface
Operation Table 14-1. QSPI Input and Output Signals and Functions Signal Name Hi-Z or Actively Driven Function QSPI Data Output (QSPI_Dout) Conﬁgurable Serial data output from QSPI QSPI Data Input (QSPI_Din) Serial data input to QSPI Serial Clock (QSPI_CLK) Actively driven Clock output from QSPI Peripheral Chip Selects (QSPI_CS[3:0]) Actively driven...
Page 342: Qspi Ram
Operation Execution continues at the internal pointer address unless the QWR[NEWQP] value is changed. After each command is executed, QWR[ENDQP] and QWR[CPTQP] are compared. When a match occurs, QIR[SPIF] is set and the QSPI stops unless wraparound mode is enabled. Setting QWR[WREN] enables wraparound mode. QWR[NEWQP] is cleared at reset.
Page 343: Receive Ram
Operation Relative Address Register Function 0x00 QTR0 Transmit RAM 0x01 QTR1 16 bits wide 0x0F QTR15 0x10 QRR0 Receive RAM 0x11 QRR1 16 bits wide 0x1F QRR15 0x20 QCR0 Command RAM 0x21 QCR1 8 bits wide 0x2F QCR15 Figure 14-2. QSPI RAM Model 14.4.1.1 Receive RAM Data received by the QSPI is stored in the receive RAM segment located at 0x10 to 0x1F in the QSPI RAM space.
Page 344: Transmit Ram
Operation 14.4.1.2 Transmit RAM Data to be transmitted by the QSPI is stored in the transmit RAM segment located at addresses 0x0 to 0xF. The user normally writes 1 word into this segment for each queue command to be executed. The user cannot read transmit RAM. Out-bound data must be written to transmit RAM in a right-justiﬁed format.
Page 345: Transfer Delays
Operation Table 14-2. QSPI_CLK Frequency as Function of CPU Clock and Baud Rate CPU Clock QMR [BAUD] 66 MHz 48 MHz 33 MHz 20 MHz 33,000,000 24,000,000 16,500,000 10,000,000 16,500,000 12,000,000 8,250,000 5,000,000 8,250,000 6,000,000 4,125,000 2,500,000 4,125,000 3,000,000 2,062,500 1,250,000 2,062,500 1,500,000...
Page 346: Transfer Length
Operation A zero value for DTL causes a delay-after-transfer value of 8192/CLKIN frequency. Standard delay after transfer = 17/CLKIN frequency (DT = 0) Adequate delay between transfers must be speciﬁed for long data streams because the QSPI module requires time to load a transmit RAM entry for transfer. Receiving devices need at least the standard delay between successive transfers.
Page 347: Programming Model
Programming Model RAM. Each time the end of the queue is reached, QIR[SPIFE] is set. QIR[SPIF] is not automatically reset. If interrupt driven QSPI service is used, the service routine must clear QIR[SPIF] to abort the current request. Additional interrupt requests during servicing can be prevented by clearing QIR[SPIFE].
Page 348 Programming Model Table 14-3 gives QMR ﬁeld descriptions. Table 14-3. QMR Field Descriptions Bits Name Description MSTR Master mode enable. 0 Reserved, do not use. 1 The QSPI is in master mode. Must be set for the QSPI module to operate correctly. DOHIE Data output high impedance enable.
Page 349: Qspi Delay Register (Qdlyr)
Programming Model QSPI_CLK QSPI_Dout QSPI_Din QSPI_CS QMR[CPOL] = 0 Chip selects are active low QMR[CPHA] = 1 A = QDLYR[QCD] QCR[CONT] = 0 B = QDLYR[DTL] Figure 14-4. QSPI Clocking and Data Transfer Example 14.5.2 QSPI Delay Register (QDLYR) Figure 14-5 shows the QSPI delay register. Field Reset 0000_0100_0000_0100...
Page 350: Qspi Wrap Register (Qwr)
Programming Model 14.5.3 QSPI Wrap Register (QWR) Field HALT WREN WRTO CSIV ENDQP NEWQP – Reset 0000_0000_0000_0000 Address MBAR + 0x00A8 Figure 14-6. QSPI Wrap Register (QWR) Table 14-5 gives QWR field descriptions. Table 14-5. QWR Field Descriptions Bits Name Description HALT Halt transfers.
Page 351 Programming Model Table 14-6 describes QIR ﬁelds. Table 14-6. QIR Field Descriptions BIts Name Description WCEFB Write collision access error enable. A write collision occurs during a data transfer when the RAM entry containing the command currently being executed is written to by the CPU with the QDR.
Page 352: Qspi Address Register (Qar)
Programming Model NOTE: The QAR does not wrap after the last queue entry within each section of the RAM. 14.5.5 QSPI Address Register (QAR) The QAR, shown in Figure 14-8, is used to specify the location in the QSPI RAM that read and write operations affect.
Page 353: Programming Example
Programming Model Field CONT BITSE DSCK QSPI_CS – Reset Undeﬁned Write Only Address QAR[ADDR] Figure 14-10. Command RAM Registers (QCR0–QCR15) Table 14-7 gives QCR ﬁeld descriptions. Table 14-7. QCR0–QCR15 Field Descriptions Bits Name Description CONT Continuous. 0 Chip selects return to inactive level deﬁned by QWR[CSIV] when transfer is complete. 1 Chip selects remain asserted after transfer is complete.
Page 354 Programming Model 5. Write QAR with 0x0020 to select the ﬁrst command RAM entry. 6. Write QDR with 0x7E00, 0x7E00, 0x7E00, 0x7E00, 0x7D00, 0x7D00, 0x7D00, 0x7D00, 0x7B00, 0x7B00, 0x7B00, 0x7B00, 0x7700, 0x7700, 0x7700, and 0x7700 to set up four transfers for each chip select. The chip selects are active low in this example.
Page 355: Timer Module
Chapter 15 Timer Module This chapter describes conﬁguration and operation of the four general-purpose timer modules, timer 0, 1, 2 and 3. 15.1 Overview The timer module has four identical general-purpose 16-bit timers and a software watchdog timer, described in Chapter 6, “System Integration Module (SIM).” Each general-purpose timer consists of a timer mode register (TMR n ), a timer capture register (TCR n ), a 16-bit timer counter (TCN n ), a timer reference register (TRR n), and a timer event register (TERn).
Page 356: Timer Operation
Timer Operation Timer 1 Timer 0 System Clock or System Clock/16 Timer Event Register (TER0) Timer Clock TIN1 Generator Timer Mode Register (TMR0) TIN0 Prescaler Mode Bits Divider Clock Timer Counter (TCN0) Capture Detection TOUT1 Timer Reference Register (TRR0) TOUT0 Interrupt (T1) Interrupt (T0) Capture Register (TCR0)
Page 357: General-Purpose Timer Registers
General-Purpose Timer Registers The maximum timer resolution is one system clock cycle (15 nS at 66 MHz). The maximum period (the reference value is all ones) is 268,435,456 cycles = 2 (4 seconds at 66 MHz). The timer can be conﬁgured to count until a reference is reached at which point it can either start a new time count immediately or continue to run.
Page 358: Timer Reference Registers (Trr0–Trr3)
General-Purpose Timer Registers Table 15-1. TMRn Field Descriptions Bits Name Description 15–8 Prescaler. Programmed to divide the clock input by values from 1 to 256. The value 0000_0000 divides the clock by 1; the value 1111_1111 divides the clock by 256. 7–6 Capture edge and enable interrupt.
Page 359: Timer Capture Registers (Tcr0–Tcr3)
General-Purpose Timer Registers 15.3.3 Timer Capture Registers (TCR0–TCR3) Each TCR is used to latch the TCN value during a capture operation when an edge occurs on the respective TIN0, TIN1, UART0_RxD, or UART1_RxD, as programmed in TMRn. Field CAP (16-bit capture counter value) Reset 0000_0000_0000_0000 Read Only...
Page 360 General-Purpose Timer Registers Table 15-2. TERn Field Descriptions Bits Name Description 15–2 — Reserved, should be cleared. Output reference event. 0 The counter has not reached the TRR value 1 The counter reached the TRR value. TMR[ORI] is used to enable the interrupt request caused by this event.
Page 361: Uart Modules
Chapter 16 UART Modules This chapter describes universal asynchronous/synchronous receiver/transmitters (UARTs) implemented on the MCF5272 and includes programming examples. All references to UART refer to one of these modules. 16.1 Overview The MCF5272 contains two independent UARTs. Each UART can be clocked by either URT_CLK or CLKIN, eliminating the need for an external crystal.
Page 362: Serial Module Overview
Serial Module Overview 16.2 Serial Module Overview The MCF5272 contains two independent UART modules, whose features are as follows: • Each clocked by either URT_CLK or CLKIN, eliminating a need for an external crystal • Full-duplex asynchronous/synchronous receiver/transmitter channel • 24-byte FIFO receiver —...
Page 363: Register Descriptions
Register Descriptions 16.3 Register Descriptions This section contains a detailed description of each register and its speciﬁc function. Flowcharts in Section 16.5.6, “Programming,” describe basic UART module programming. The operation of the UART module is controlled by writing control bytes into the appropriate registers.
Page 364 Register Descriptions Table 16-1. UART Module Programming Model (Continued) MBAR Offset [31:24] [23:16] [15:8] [7:0] UART0 UART1 0x11C 0x15C (Read) Do not access. — UART divider lower — registers—(UDLn) [p. 16-14] 0x120 0x160 (Read) UART autobaud — register MSB—(UABUn) [p. 16-18] (Write) Do not access.
Page 365: Uart Mode Registers 1 (Umr1N)
Register Descriptions 16.3.1 UART Mode Registers 1 (UMR1n) The UART mode registers 1 (UMR1n) control conﬁguration. UMR1n can be read or written when the mode register pointer points to it, at RESET or after a RESET MODE command using UCRn[MISC]. After UMR1n is read or written, the REGISTER POINTER pointer points to UMR2n.
Page 366: Uart Mode Register 2 (Umr2N)
Register Descriptions Table 16-2. UMR1n Field Descriptions (Continued) Bits Name Description Parity type. PM and PT together select parity type (PM = 0x) or determine whether a data or address character is transmitted (PM = 11). Parity Mode Parity Type (PT= 0) Parity Type (PT= 1) With parity Even parity...
Page 367: Uart Status Registers (Usrn)
Register Descriptions Table 16-3. UMR2n Field Descriptions Bits Name Description 7–6 Channel mode. Selects a channel mode. Section 16.5.3, “Looping Modes,” describes individual modes. 00 Normal 01 Automatic echo 10 Local loop-back 11 Remote loop-back TxRTS Transmitter ready-to-send. Controls negation of RTS to automatically terminate a message transmission when the transmitter is disabled after completion of a transmission.
Page 368: Uart Clock-Select Registers (Ucsrn)
Register Descriptions Table 16-4 describes USRn ﬁelds. Table 16-4. USRn Field Descriptions Bits Name Description Received break. The received break circuit detects breaks that originate in the middle of a received character. However, a break in the middle of a character must persist until the end of the next detected character time.
Page 369: Uart Command Registers (Ucrn)
Register Descriptions Field Reset 0000_0000 Write only Address MBAR + 0x104 (UCSR0), 0x144 (UCSR1) Figure 16-5. UART Clock-Select Registers (UCSRn) Table 16-5 describes UCSRn ﬁelds. Table 16-5. UCSRn Field Descriptions Bits Name Description 7–4 Receiver clock select. Selects the clock source for the receiver channel. 1101 Prescaled CLKIN 1110 URT_CLK divided by 16 1111 URT_CLK...
Page 370 Register Descriptions Table 16-6. UCRn Field Descriptions Bits Value Command Description ENAB — Enable autobaud 0 Autobaud disabled. 1 Autobaud enabled. The transmission rate is calculated from the ﬁrst received character. If the rate must be recalculated, ENAB must ﬁrst be cleared and reset.
Page 371: Uart Receiver Buffers (Urbn)
Register Descriptions Table 16-6. UCRn Field Descriptions (Continued) Bits Value Command Description 1–0 RC (This ﬁeld selects a single command) Causes the receiver to stay in its current mode. If the receiver is enabled, it NO ACTION TAKEN remains enabled; if disabled, it remains disabled. If the UART module is not in multidrop mode (UMR1n[PM] ≠...
Page 372: Uart Input Port Change Registers (Uipcrn)
Register Descriptions Field Reset 0000_0000 Write only Address MBAR + 0x10C,0x14C Figure 16-8. UART Transmitter Buffers (UTBn) 16.3.8 UART Input Port Change Registers (UIPCRn) The input port change registers (UIPCRn), Figure 16-9, hold the current state and the change-of-state for CTS. Field —...
Page 373: Uart Interrupt Status/Mask Registers (Uisrn/Uimrn)
Register Descriptions Field — RTSL Reset 0000_0000 Write only Address MBAR + 0x110 (UACR0), 0x150 (UACR1) Figure 16-10. UART Auxiliary Control Registers (UACRn) Table 16-8 describes UACRn ﬁelds. Table 16-8. UACRn Field Descriptions Bits Name Description 7–3 — Reserved, should be cleared. 2–1 RTSL RTS level.
Page 374: Uart Divider Upper/Lower Registers (Udun/Udln)
Register Descriptions Table 16-9 describes UISRn and UIMRn ﬁelds. Table 16-9. UISRn/UIMRn Field Descriptions Bits Name Description Change-of-state. 0 UIPCRn[COS] is not selected. 1 Change-of-state occurred on CTS and was programmed in UACRn[IEC] to cause an interrupt. Autobaud calculation. 0 Autobaud is disabled or is waiting for the ﬁrst receiver character. 1 The baud rate has been calculated and loaded into the clock source divider (UDUn and UDLn).
Page 375: Uart Autobaud Registers (Uabun/Uabln)
Register Descriptions Field Divider LSB Reset 0000_0000 Write only Address MBAR + 0x11C (UDL0), 0x15C (UDL1) Figure 16-13. UART Divider Lower Registers (UDLn) NOTE: The minimum value that can be loaded on the concatenation of UDUn with UDLn is 0x0002. Both UDUn and UDLn are write-only and cannot be read by the CPU.
Page 376: Uart Receiver Fifo Registers (Urfn)
Register Descriptions Field FULL Reset 1100_0000 Address MBAR + 0x128 (UTF0), 0x168 (UTF1) Figure 16-16. UART Transmitter FIFO Registers (UTFn) Table 16-10 describes UTFn ﬁelds. Table 16-10. UTFn Field Descriptions Bits Name Description 7–6 Transmitter status. When written to, these bits control the meaning of UISRn[TxFIFO]. 00 Inhibit transmitter FIFO status indication in UISRn.
Page 377: Uart Fractional Precision Divider Control Registers (Ufpdn)
Register Descriptions Table 16-11. URFn Field Descriptions Bits Name Description 7–6 Receiver status. When written to, these bits control the meaning of UISRn[RxFIFO]. 00 Inhibit receiver FIFO status indication in UISRn. 01 Receiver FIFO ≥ 25% full 10 Receiver FIFO ≥ 50% full 11 Receiver FIFO ≥...
Page 378: Uart Input Port Registers (Uipn)
Register Descriptions 16.3.16 UART Input Port Registers (UIPn) The UIP registers, Figure 16-19, show the current state of the CTS input. Field — Reset 1111_1111 Read only Address MBAR + 0x134 (UIP0), 0x174 (UIP1) Figure 16-19. UART Input Port Registers (UIPn) Table 16-13 describes UIPn ﬁelds.
Page 379 UART Module Signal Deﬁnitions 16.4 UART Module Signal Deﬁnitions Figure 16-21 shows both the external and internal signal groups. CLKIN Clock Source Generator External clock (URT_CLK) URT_RTS Output Port UART Module URT_CTS Internal Bus Input Port Control External Internal Interface Control URT_RxD Signals...
Page 380: Operation
Operation Table 16-15. UART Module Signals (Continued) Signal Description Request-to- This output can be programmed to be negated or asserted automatically by either the receiver Send (URT_RTS) or the transmitter. It can control serial data ﬂow when connected to a transmitter’s CTS. Clock (URT_CLK) The UART’s external clock source.
Page 381: Calculating Baud Rates
Operation Note that when autobaud mode is enabled, the UFPDn, UDUn, and UDLn are automatically loaded with the calculated baud rate. However, the calculated value can be overridden by a programmed value at any time. The choice of URT_CLK or CLKIN is programmed in the UCSR. URT_CLK UART Clocking sources programmed in UCSR...
Page 382: External Clock
Operation 3. Using the formula Fractional Divider = (truncated remainder * 16) = 0.52 * 16 = 8.32 = 8 (truncate to nearest whole number) UFPD = 0x08 4. This now gives an effective total error in the baud rate as: %Error = 100 x (Truncated remainder) / (16 x (UD + UFPD/16)] = 100 x 0.32 / (16 x (6 + 8/16)) = 32 / 104...
Page 383: Transmitter And Receiver Operating Modes
Operation 16.5.2 Transmitter and Receiver Operating Modes Figure 16-24 is a functional block diagram of the transmitter and receiver showing the command and operating registers, which are described generally in the following sections and described in detail in Section 16.3, “Register Descriptions.” UART UART Command Register (UCR0) UART Mode Register 1 (UMR1)
Page 384 Operation If the clear-to-send operation is enabled, CTS must be asserted for the character to be transmitted. If CTS is negated in the middle of a transmission, the character in the shift register is sent and TxD remains in mark state until CTS is reasserted. If the transmitter is forced to send a continuous low condition by issuing a command, the START BREAK...
Page 385: Receiver
Operation 16.5.2.2 Receiver The receiver is enabled through its UCRn, as described in Section 16.3.5, “UART Command Registers (UCRn).” Figure 16-26 shows receiver functional timing. C26, C27, and C82 are lost Receiver Enabled USRn[RxRDY] USRn[FFULL] internal module select Status Status Status Status Data...
Page 386: Transmitter Fifo
Operation If a break condition is detected (RxD is low for the entire character including the stop bit), a character of all zeros is loaded into the receiver holding register (RHR) and USRn[RB,RxRDY] are set. RxD must return to a high condition for at least one-half bit time before a search for the next start bit begins.
Page 387 Operation The two error modes are selected by UMR1n[ERR] as follows: • In character mode (UMR1n[ERR] = 0), status is given in the USRn for the character at the top of the FIFO. • In block mode, the USRn shows a logical OR of all characters reaching the top of the FIFO stack since the last command.
Page 388: Looping Modes
Operation 16.5.3 Looping Modes The UART can be conﬁgured to operate in various looping modes as shown in Figure 16-26. These modes are useful for local and remote system diagnostic functions and are described in the following paragraphs and in Section 16.3, “Register Descriptions.” The UART’s transmitter and receiver should be disabled when switching between modes, as the selected mode is activated immediately upon mode selection, regardless of whether a character is being received or transmitted.
Page 389: Remote Loop-Back Mode
Operation 16.5.3.3 Remote Loop-Back Mode In remote loop-back mode, shown in Figure 16-29, the channel automatically transmits received data bit by bit on the TxD output. The local CPU-to-transmitter link is disabled. This mode is useful in testing receiver and transmitter operation of a remote channel. For this mode, the transmitter uses the receiver clock.
Page 390 Operation Master Station ADD1 ADD2 Transmitter Enabled USRn[TxRDY] internal module select UMR1n[PM] = 11 ADD 1 ADD 2 UMR1n[PT] = 1 UMR1n[PT] = 0 UMR1n[PT] = 2 Peripheral Station ADD1 ADD2 Receiver Enabled USRn[RxRDY] internal module select UMR1n [PM] = 11 ADD 1 Status Data Status Data...
Page 391: Bus Operation
Operation 16.5.5 Bus Operation This section describes bus operation during read, write, and interrupt acknowledge cycles to the UART module. 16.5.5.1 Read Cycles The UART module responds to reads with byte data. Reserved registers return zeros. 16.5.5.2 Write Cycles The UART module accepts write data as bytes. Write cycles to read-only or reserved registers complete normally without exception processing, but data is ignored.
Page 392: Uart Module Initialization Sequence
Operation 16.5.6.1 UART Module Initialization Sequence NOTE: UART module registers can be accessed by word or byte operations, but only data byte D[7:0] is valid. Figure 16-31 shows the UART module initialization sequence. ENABLE ENABLA SERIAL MODULE ERRORS SINIT INITIATE: CHANNEL INTERRUPTS ENABLE RECEIVER...
Page 393 Operation CHCHK CHCHK PLACE CHANNEL IN LOCAL LOOPBACK MODE ENABLE TRANSMITTER CLEAR STATUS WORD TxCHK WAITED SET TRANSMITTER- TRANSMITTER TOO LONG NEVER-READY FLAG READY SNDCHR SEND CHARACTER TO TRANSMITTER RxCHK WAITED SET RECEIVER- CHARACTER BEEN TOO LONG NEVER-READY FLAG RECEIVED Figure 16-31.
Page 394 Operation FRCHK RSTCHN DISABLE HAVE TRANSMITTER FRAMING ERROR RESTORE TO ORIGINAL MODE SET FRAMING ERROR FLAG PRCHK RETURN HAVE PARITY ERROR SET PARITY ERROR FLAG CHRCHK GET CHARACTER FROM RECEIVER SAME AS TRANSMITTED CHARACTER SET INCORRECT CHARACTER FLAG Figure 16-31. UART Mode Programming Flowchart (Sheet 3 of 5) 16-34 MCF5272 User’s Manual...
Page 395 Operation SIRQ INCH ABRKI DOES CHANNEL A IRQ CAUSED RECEIVER HAVE A BY BEGINNING CHARACTER OF A BREAK PLACE CHARACTER CLEAR CHANGE-IN- IN D0 BREAK STATUS BIT ABRKI1 RETURN END-OF-BREAK IRQ ARRIVED CLEAR CHANGE-IN- BREAK STATUS BIT REMOVE BREAK CHARACTER FROM RECEIVER FIFO REPLACE RETURN ADDRESS ON SYSTEM...
Page 396 Operation OUTCH TRANSMITTER READY SEND CHARACTER TO TRANSMITTER RETURN Figure 16-31. UART Mode Programming Flowchart (Sheet 5 of 5) 16-36 MCF5272 User’s Manual...
Page 397: Overview
Chapter 17 General Purpose I/O Module This chapter describes the operation and programming model of the three general-purpose I/O (GPIO) ports on the MCF5272. It includes details about pin assignment, direction-control, and data registers.. 17.1 Overview The MCF5272 provides up to 48 general-purpose I/O signals. Eight general-purpose I/O pins are always available, the rest are multiplexed as shown in Table 17-1.
Page 398: Port Control Registers
Port Control Registers 17.2 Port Control Registers The port control registers are used to conﬁgure all pins that carry signals multiplexed from different on-chip modules. Each pin is conﬁgured with a two-bit ﬁeld. Pin functions are referred to as function 0b00–0b11. The function 0 signals corresponding to GPIO ports A and B are immediately available after reset.
Page 399 Port Control Registers Field PACNT15 PACNT14 PACNT13 PACNT12 PACNT11 PACNT10 PACNT9 PACNT8 Reset 0000_0000_0000_0000 Read/Write Field PACNT7 PACNT6 PACNT5 PACNT4 PACNT3 PACNT2 PACNT1 PACNT0 Reset 0000_0000_0000_0000 Read/Write Addr MBAR + 0x0080 Figure 17-1. Port A Control Register (PACNT) Table 17-3 describes PACNT ﬁelds. Table 17-4 provides the same information organized by function.
Page 400 Port Control Registers Table 17-3. PACNT Field Descriptions (Continued) Bits Name Description (Continued) 17–16 PACNT8 Conﬁgure pin J2 00 PA8 01 FSC0/FSR0 1x Reserved 15–14 PACNT7 Conﬁgure pin P1 00 PA7 01 QSPI_CS3 10 DOUT3 11 Reserved 13–12 PACNT6 Conﬁgure pin E1 00 PA6 01 USB_RxD 1x Reserved...
Page 401: Port B Control Register (Pbcnt)
Port Control Registers Table 17-4. Port A Control Register Function Bits (Continued) PACNT[xx] = 00 PACNT[xx] = 01 PACNT[xx] = 10 PACNT[xx] = 11 Number (Function 0b00) (Function 0b01) (Function 0b10) (Function 0b11) USB_RN – – USB_TN – – USB_Susp –...
Page 402 Port Control Registers Table 17-5. PBCNT Field Descriptions Bits Name Description 31–30 PBCNT15 Conﬁgure pin P10 00 PB15 01 E_MDC 1x Reserved 29–28 PBCNT14 Conﬁgure pin L9 00 PB14 01 E_RxER 1x Reserved 27–26 PBCNT13 Conﬁgure pin M9 00 PB13 01 E_RxD1 1x Reserved 25–24...
Page 403 Port Control Registers Table 17-5. PBCNT Field Descriptions (Continued) Bits Name Description (Continued) 7–6 PBCNT3 Conﬁgure pin H3 00 PB3 01 URT0_RTS 1x Reserved 5–4 PBCNT2 Conﬁgure pin H2 00 PB2 01 URT0_CTS 1x Reserved 3–2 PBCNT1 Conﬁgure pin H1. The signal URT0_RxD is always internally connected to TIN3. 00 PB1 01 URT0_RxD/TIN3 1x Reserved...
Page 404: Port C Control Register
Port Control Registers 17.2.3 Port C Control Register There is no port C control register. Port C is enabled only when the external data bus is 16 bits wide. This is done by holding QSPI_DOUT/WSEL high during reset. When QSPI_DOUT/WSEL is low during reset, the external data bus is 32 bits wide and port C is unavailable.
Page 405: Data Direction Registers
Data Direction Registers Table 17-7. PDCNT Field Descriptions (Continued) Bits Name Description (Continued) 9–8 PDCNT4 Conﬁgure pin K1. 00 High impedance 01 DOUT0 10 URT1_TxD 11 Reserved 7–6 PDCNT3 Conﬁgure pin K3. 00 High impedance 01 Reserved 10 URT1_RTS 11 INT5 5–4 PDCNT2 Conﬁgure pin K2.
Page 406: Port A Data Direction Register (Paddr)
Data Direction Registers the appropriate control register. If a GPIO line changes from an input to an output, the initial data on that pin is the last data written to the latch by the corresponding data register. At system reset, these register bits are all cleared, conﬁguring all port I/O lines as general purpose inputs.
Page 407: Port C Data Direction Register (Pcddr)
Port Data Registers 17.3.3 Port C Data Direction Register (PCDDR) The PCDDR determines the signal direction of each parallel port pin programmed as a GPIO port in the PCCNT. Field PCDDR Reset 0000_0000_0000_0000 Read/Write Addr MBAR + 0x0094 Figure 17-6. Port C Data Direction Register (PCDDR) 17.4 Port Data Registers These 16-bit bidirectional registers are used to read or write the logic states of the GPIO lines.
Page 408: Port Data Register (Pxdat)
Port Data Registers 17.4.1 Port Data Register (PxDAT) In the following description PxDAT refers to PADAT, PBDAT, or PCDAT. The PxDAT value for inputs corresponds to the logic level at the pin; for outputs, the value corresponds to the logic level driven onto the pin. Note that PxDAT has no effect on pins which have not been conﬁgured for GPIO.
Page 409: Overview
Chapter 18 Pulse Width Modulation (PWM) Module This chapter describes the conﬁguration and operation of the pulse width modulation (PWM) module. It includes a block diagram, programming model, and timing diagram. 18.1 Overview The PWM module shown in Figure 18-1, generates a synchronous series of pulses having programmable duty cycle.
Page 410: Pwm Operation
PWM Operation Summary of the main features include: • Double-buffered width register • Variable-divide prescale • Three independent PWM modules • Byte-wide width register provides programmable duty cycle control 18.2 PWM Operation The PWM is a simple free-running counter combined with a pulse width register and a comparator such that the output is cleared whenever the counter value exceeds the width register value.
Page 411: Pwm Control Register (Pwcrn)
PWM Programming Model 18.3.1 PWM Control Register (PWCRn) This register, shown in Figure 18-2, controls the overall operation of the PWM. Unless disabled and then re-enabled, writing to PWCR while the PWM is running will not alter its operation until the current output cycle ﬁnishes. For example, if the prescale value is changed while the PWM is enabled, the new value will not take effect until after the counter has “wrapped around”.
Page 412: Pwm Width Register (Pwwdn)
PWM Programming Model 18.3.2 PWM Width Register (PWWDn) This register, shown in Figure 18-3, controls the width of the output pulse. When the counter become greater than or equal to the value in this register, the output is cleared for the remainder of the period.
Page 413 PWM Programming Model 256T PWWD[PW] = 0x00 255T PWWD[PW] = 0x01 128T PWWD[PW] = 0x80 128T PWWD[PW] = 0xFF 255T PWCR n [FRC1] = 1 PWCRn[CKSL] = 0000: T = 1 x CPU clock period PWCR n [CKSL] = 1111: T = 32768 x CPU clock period Figure 18-4.
Page 414 PWM Programming Model 18-6 MCF5272 User’s Manual...
Page 415: Signal Descriptions
Chapter 19 Signal Descriptions This chapter provides a listing and brief description of all the MCF5272 signals. It shows it shows which are inputs or outputs, how they are multiplexed, and the state of each signal at reset. The ﬁrst listing is organized by function with signals appearing alphabetically within each functional group.
Page 416 Signal List Table 19-1. Signal Descriptions Sorted by Function (Continued) Conﬁgured Pin Functions Drive Description (mA) 0 (Reset) (see notes) – – – – – – – – – – – – SDA1 SDA0 – A2/SDRAM-16bit A1/SDRAM-32bit A0 – – –...
Page 417 Signal List Table 19-1. Signal Descriptions Sorted by Function (Continued) Conﬁgured Pin Functions Drive Description (mA) 0 (Reset) (see notes) WSEL pin – – D0/port C bit 0 WSEL pin – – D1/port C bit 1 WSEL pin PC10 – –...
Page 418 Signal List Table 19-1. Signal Descriptions Sorted by Function (Continued) Conﬁgured Pin Functions Drive Description (mA) 0 (Reset) (see notes) DCL1/ – – – PLIC ports 1, 2, 3 data GDCL1_OUT clock/Generated DCL DDATA0 – – – Debug data 0 DDATA1 –...
Page 419 Signal List Table 19-1. Signal Descriptions Sorted by Function (Continued) Conﬁgured Pin Functions Drive Description (mA) 0 (Reset) (see notes) Port D Cntl High Z – URT1_ QSPI_ UART1 CTS/QSPI_CS2 Port D Cntl High Z – URT1_RTS INT5 UART1 RTS/INT5 Port D Cntl High Z DOUT0...
Page 420 Signal List Table 19-1. Signal Descriptions Sorted by Function (Continued) Conﬁgured Pin Functions Drive Description (mA) 0 (Reset) (see notes) Port A Cntl USB_ – – Port A bit 4/ Susp Suspend USB driver Port A Cntl USB_TxEN – – Port A bit 5/USB transmitter enable Port A Cntl...
Page 421 Signal List Table 19-1. Signal Descriptions Sorted by Function (Continued) Conﬁgured Pin Functions Drive Description (mA) 0 (Reset) (see notes) Port B Cntl – – – Port B bit 6 Port B Cntl TOUT0 – – Port B bit 7/Timer 0 output compare Port B Cntl E_TxD3...
Page 422 Signal List Table 19-1. Signal Descriptions Sorted by Function (Continued) Conﬁgured Pin Functions Drive Description (mA) 0 (Reset) (see notes) BYPASS – – – Bypass internal test mode MTMOD PSTCLK – – JTAG test clock in/ BDM PSTCLK output MTMOD –...
Page 423 Signal List Table 19-2. Signal Name and Description by Pin Number Pin Functions Name Description 0 (Reset) DDATA3 – – – DDATA3 Debug data 3 DDATA1 – – – DDATA1 Debug data 1 – – – BDM debug transfer error acknowledge –...
Page 424 Signal List Table 19-2. Signal Name and Description by Pin Number (Continued) Pin Functions Name Description 0 (Reset) SDA5 SDA4 – A6/SDA5/SDA4 A6/SDRAM-16bit A5/SDRAM-32bit A4 PST2 – – – PST2 Internal processor status 2 PST1 – – – PST1 Internal processor status 1 DDATA0 –...
Page 425 Signal List Table 19-2. Signal Name and Description by Pin Number (Continued) Pin Functions Name Description 0 (Reset) SDA9 SDA8 – A10/SDA9/SDA8 A10/SDRAM-16bit A9/SDRAM-32bit A8 SDCLKE – – – SDCLKE SDRAM clock enable A10_PRECHG – – – A10_PRECHG SDRAM A10_Precharge USB_RxD –...
Page 426 Signal List Table 19-2. Signal Name and Description by Pin Number (Continued) Pin Functions Name Description 0 (Reset) F10] +3.3V PC12 – – D12/PC12 D12/port C bit 12 – – D24/D8 D24/D8 – – D25/D9 D25/D9 – – D26/D10 D26/D10 USB_VDD –...
Page 427 Signal List Table 19-2. Signal Name and Description by Pin Number (Continued) Pin Functions Name Description 0 (Reset) – – D31/D15 D31/D15 – – D30/D14 D30/D14 USB_CLK – – – USB_CLK USB external 48-MHz clock input FSC0/ – – PA8/FSC0/FSR0 Port A bit 8/IDL FSR0 &...
Page 428 Signal List Table 19-2. Signal Name and Description by Pin Number (Continued) Pin Functions Name Description 0 (Reset) – – D6/PC6 D6/port C bit 6 PA11 – QSPI_CS1 – PA11/QSPI_CS1 Port A bit 11/QSPI chip select 1 PA12 DFSC2 – –...
Page 429 Signal List Table 19-2. Signal Name and Description by Pin Number (Continued) Pin Functions Name Description 0 (Reset) E_RxDV – – – E_RxDV Ethernet Rx data valid E_TxD2 – – PB9/E_TxD2 Port B bit 9/Tx data bit 2 (100 Base-T Ethernet only) PB13 E_RxD1...
Page 430: Address Bus (A[22:0]/Sdram_Adr[13:0])
Address Bus (A[22:0]/SDRAM_ADR[13:0]) Table 19-2. Signal Name and Description by Pin Number (Continued) Pin Functions Name Description 0 (Reset) QSPI_CS3 DOUT3 – PA7/QSPI_CS3/DOUT3 PA7/QSPI chip select 4/PLIC port 3 data output High Z – DIN3 INT4 DIN3/INT4 Interrupt 4 input/PLIC port 3 data input INT2 –...
Page 431: Dynamic Data Bus Sizing
Chip Selects (CS7/SDCS, CS6/AEN, CS[5:1], CS0) When a 16-bit data bus is used, mode parallel port C pins can be multiplexed onto D[15:0]. Data read from or written to on-chip peripherals is visible on the external data bus when the device’s external bus width is 32 bits.
Page 432 Bus Control Signals peripheral accesses, these outputs indicate that data is to be latched or driven onto a byte of the data when driven low. BSn signals are asserted only to the memory bytes used during a read or write access. BSn signals are asserted during accesses to on-chip peripherals but not to on-chip SRAM, cache, or ROM.
Page 433: Read/Write (R/W)
Bus Control Signals Table 19-5. Connecting BS[3:0] to DQMx 5272 SDRAM Data Signals 16 Bit 32 Bit 16 Bit 32 Bit (2 x 16) 32 Bit (1 x 32) DQMH DQMH DQM3 D[31:24] DQML DQML DQM2 D[23:16] DQMH DQM1 D[15:8] DQML DQM0 D[7:0]...
Page 434: Bypass
CPU Clock and Reset Signals 19.5.6 Bypass Bypass is a Motorola test mode signal. This signal should be left unconnected. 19.5.7 SDRAM Row Address Strobe (RAS0) RAS0 is the SDRAM row address strobe output. 19.5.8 SDRAM Column Address Strobe (CAS0) CAS0 is the SDRAM column address strobe output.
Page 435: Dreseten
Interrupt Request Inputs (INT[6:1]) 19.6.2 DRESETEN DRESETEN is asserted to indicate that the SDRAM controller is to be reset whenever RSTI asserts. If DRESETEN is high, RSTI does not affect the SDRAM controller, which continues to refresh external memory. This is useful for debug situations where a reset of the device is required without losing data located in SDRAM.
Page 436: Uart0 Module Signals And Pb[4:0]
UART0 Module Signals and PB[4:0] pin. After reset all pins multiplexed with GPIO signals default to inputs. Port A general purpose I/O, PA[15:8] are multiplexed with PLIC TDM port 1 pins. Port A general purpose I/O, PA[6:0] are multiplexed with USB module signals. PA7 is multiplexed with QSPI_CS3 and DOUT3.
Page 437: Request To Send (Urt0_Rts/Pb3)
USB Module Signals and PA[6:0] 19.9.4 Request to Send (URT0_RTS/PB3) UART0 mode: Asserting URT0_RTS output is an automatic request to send output from the UART0 module. URT0_RTS can also be conﬁgured to be asserted and negated as a function of the RxFIFO level. Port B mode: This pin can also be conﬁgured as the PB3 I/O.
Page 438: Usb Transmitter Output Enable (Usb_Txen/Pa5)
USB Module Signals and PA[6:0] 19.10.6 USB Transmitter Output Enable (USB_TxEN/PA5) USB mode: USB_TxEN enables the transceiver to transmit data on the bus. It requires a 4.7-KΩ pullup resistor to ensure that the external USB Tx driver is off between the MCF5272 coming out of reset and initializing the port A pin conﬁguration register.
Page 439: Timer Module Signals
Timer Module Signals 19.11 Timer Module Signals This section describes timer module signals. 19.11.1 Timer Input 0 (TIN0) The timer input (TIN0) can be programmed to cause events to occur in timer counter 1. It can either clock the event counter or provide a trigger to the timer value capture logic. 19.11.2 Timer Output (TOUT0)/PB7 Timer mode: Timer output (TOUT0) is the output from timer 0.
Page 440: Collision (E_Col)
Ethernet Module Signals 19.12.3 Collision (E_COL) The E_COL input is asserted upon detection of a collision and remains asserted while the collision persists. This signal is not deﬁned for full-duplex mode. 19.12.4 Receive Data Valid (E_RxDV) Asserting the receive data valid (E_RxDV) input indicates that the PHY has valid nibbles present on the MII.
Page 441: Receive Error (E_Rxer/Pb14)
PWM Module Signals (PWM_OUT0–PWM_OUT2]) 19.12.10 Receive Error (E_RxER/PB14) Ethernet mode: E_RxER is an input signal which when asserted along with E_RxDV signals that the PHY has detected an error in the current frame. When E_RxDV is not asserted E_RxER has no effect. Applies to MII mode operation. Port B mode: This pin can also be conﬁgured as PB14 I/O.
Page 442: Queued Serial Peripheral Interface (Qspi) Signals
Queued Serial Peripheral Interface (QSPI) Signals 19.14 Queued Serial Peripheral Interface (QSPI) Signals This section describes signals used by the queued serial peripheral interface (QSPI) module. Four QSPI chip selects, QSPI_CS[3:0], are multiplexed with the physical layer interface pins and GPIO port A. QSPI_CS0 is always available. QSPI_CS3 is multiplexed with DOUT3 and PA7.
Page 443: Synchronous Peripheral Chip Select 2 (Qspi_Cs2/Urt1_Cts)
Physical Layer Interface Controller TDM Ports 19.14.6 Synchronous Peripheral Chip Select 2 (QSPI_CS2/URT1_CTS) See Section 19.15.1.5, “UART1 CTS (URT1_CTS/QSPI_CS2).” 19.14.7 Synchronous Peripheral Chip Select 3 (PA7/DOUT3/QSPI_CS3) Section 19.15.3.3, “QSPI_CS3, Port GCI/IDL Data (PA7/DOUT3/QSPI_CS3).” See description for GPIO ports. QSPI_CS3 can be programmed to be active high or low. 19.15 Physical Layer Interface Controller TDM Ports The MCF5272 has four dedicated physical layer interface ports for connecting to external ISDN transceivers, CODECs and other peripherals.
Page 444: Data Clock (Dcl0/Urt1_Clk)
Physical Layer Interface Controller TDM Ports 19.15.1.3 Data Clock (DCL0/URT1_CLK) IDL mode: This pin is the clock used to clock data in and out of DIN0 and DOUT0 for IDL port 0. Data is clocked into DIN0 on the falling edge and clocked out of DOUT0 on the rising edge of DCL0.
Page 445: D-Channel Request(Dreq0/Pa10)
Physical Layer Interface Controller TDM Ports 19.15.1.8 D-Channel Request(DREQ0/PA10) IDL mode: This pin can be independently conﬁgured as the DREQ0 output for signaling to a layer-1 S/T transceiver that a frame of data is ready to be sent on the port 0 D channel. Port A mode: In GCI or IDL modes this pin can be independently conﬁgured as PA10.
Page 446: Gci/Idl Frame Sync (Fsc1/Fsr1/Dfsc1)
Physical Layer Interface Controller TDM Ports 19.15.2.4 GCI/IDL Frame Sync (FSC1/FSR1/DFSC1) IDL mode: FSR1 is an input for the 8-KHz frame sync for port 1. GCI mode: FSC1 is an input for the 8-KHz frame sync for port 1. Normally the GCI FSC signal is two clocks wide and is aligned with the ﬁrst B channel bit of the GCI frame.
Page 447: Gci/Idl Delayed Frame Sync 2 (Dfsc2/Pa12)
Physical Layer Interface Controller TDM Ports 19.15.3.1 GCI/IDL Delayed Frame Sync 2 (DFSC2/PA12) IDL/GCI Modes: DFSC2 is used as a programmable delayed frame sync for external IDL/GCI devices that use port 2 but are connected to the port 1 data pins. Port 2 uses the DFSC2 frame sync internally to ensure alignment with external devices synchronized with DFSC2.
Page 448: Jtag Test Access Port And Bdm Debug Port
Interrupt mode: This signal can be conﬁgured as interrupt input 4. 19.16 JTAG Test Access Port and BDM Debug Port The MCF5272 supports the Motorola background debug mode (BDM) for ColdFire processors. It also supports a JTAG test interface. The following signals do not support JTAG due to the critical timing required to support SDRAM memory: BS[3:0], RAS0, CAS0, SDCLK, SDCLKE, SDRAMCS/CS7, SDWE, A10_PRECHG, SDBA[1:0], D[31:0], A[15:0].
Page 449: Test And Debug Data In (Tdi/Dsi)
BDM mode: DSCLK is the BDM serial data clock input. It requires a 10-KΩ pullup resistor. 19.16.6 Motorola Test Mode Select (MTMOD) MTMOD: When the MTMOD input is low, JTAG mode is enabled. When it is high, BDM mode is enabled.
Page 450: Debug Data (Ddata[3:0])
The MCF5272 has four mode-select signals, some of which are shared with output signals used during normal device operation. These signals are HI-Z, QSPI_Dout/WSEL, QSPI_CLK/BUSW1, and QSPI_CS0/BUSW0. BYPASS is a Motorola test mode signal and should never have a pull-down resistor. The remaining three mode-select signals must each have a 4.7-KΩ...
Page 451: Power Supply Pins
Power Supply Pins Table 19-8. MCF5272 CS0 Memory Bus Width Selection (Continued) BUSW1 BUSW0 CS0 Bus Width 16 bits Reserved, do not use. Table 19-9. MCF5272 High Impedance Mode Selection HI-Z Data Bus Width Enable HI-Z mode, all pins are high impedance Normal operation 19.18 Power Supply Pins A pair of VDD/GND pins is dedicated to the on-chip USB transceiver.
Page 452 Power Supply Pins 19-38 MCF5272 User’s Manual...
Page 453: Bus Operation
Chapter 20 Bus Operation The MCF5272 bus interface supports synchronous data transfers that can be terminated synchronously or asynchronously and also can be burst or burst-inhibited between the MCF5272 and other devices in the system. This chapter describes the functioning of the bus for data-transfer operations, error conditions, bus arbitration, and reset operations.
Page 454: Address Bus (A[22:0])
Bus And Control Signals Table 20-1. ColdFire Bus Signal Summary (Continued) Signal Name Description Output enable Read/write Transfer acknowledge Transfer error acknowledge 20.2.1 Address Bus (A[22:0]) These output signals provide the location of a bus transfer. The address can be external SRAM, ROM, FLASH, SDRAM, or peripherals.
Page 455: Transfer Acknowledge (Ta)
Bus And Control Signals 20.2.4 Transfer Acknowledge (TA) This active-low synchronous input signal indicates the successful completion of a requested data transfer operation. During MCF5272-initiated transfers, transfer acknowledge (TA) is an asynchronous input signal from the referenced slave device indicating completion of the transfer.
Page 456: Transfer Error Acknowledge (Tea)
Bus Exception: Double Bus Fault The MCF5272 edge-detects and retimes the TA input. This means that an additional wait state may or may not be inserted. For example if the active chip select is used to immediately generate the TA input, one or two wait states may be inserted in the bus access. The TA signal function is not available after reset.
Page 457: Bus Characteristics
Bus Characteristics 20.4 Bus Characteristics The MCF5272 uses the address bus (A[22:0]) to specify the location for a data transfer and the data bus (D[31:0] or D[31:16]) to transfer the data. Control signals indicate the direction of the transfer. The selected device or the number of wait states programmed in the chip select base registers (CSBRs), the chip select option registers (CSORs), the SDRAM conﬁguration and SDRAM timing registers (SDCR, SDTR) control the length of the cycle.
Page 458: Bus Sizing
Data Transfer Mechanism 20.5.1 Bus Sizing The MCF5272 can be conﬁgured for an external physical data bus width of 16 bits by pulling QSPI_Dout/WSEL high, or for 32 bits by pulling QSPI_Dout/WSEL low during reset. When the external physical address bus size is conﬁgured for 16 bits, the signals D[15:0] become general purpose I/O port C.
Page 459 Data Transfer Mechanism REGISTER INTERNAL TO MCF5272 MULTIPLEXER ROUTING AND DUPLICATION EXTERNAL D[31:24] D[23:16] D[15:8] D[7:0] DATA BUS ADDRESS BYTE 0 BYTE 1 BYTE 2 BYTE 3 32-BIT PORT BYTE 0 BYTE 1 16-BIT PORT BYTE 2 BYTE 3 BYTE 0 BYTE 1 8-BIT PORT BYTE 2...
Page 460 Data Transfer Mechanism Table 20-3. Data Bus Byte Strobes (Continued) Transfer Size Port Size A[1:0] D[31:24] D[23:16] D[15:8] D[7:0] Word 8-bit (not supported SDRAM) 16-bit 32-bit Longword 8-bit (not supported SDRAM) 16-bit 32-bit Line 8-bit (not supported SDRAM) 16-bit 32-bit Table 20-4 lists the bytes that should be driven on the data bus during read cycles by the external peripheral device being accessed.
Page 461 Data Transfer Mechanism Table 20-4. Data Bus Requirement for Read Cycles External Data Bytes Required Transfer Size A[1:0] 32-Bit Port 16-Bit Port 8-Bit Port D[31:24] D[23:16] D[15:8] D[7:0] D[31:24] D[23:16] D[31:24] Byte Byte 0 Byte 0 Byte 0 Byte 1 Byte 1 Byte 1 Byte 2...
Page 462: External Bus Interface Types
External Bus Interface Types Table 20-5. Internal to External Data Bus Multiplexer–Write Cycle (Continued) External Data Bus Connection Transfer Size A[1:0] D[31:24] D[23:16] D[15:8] D[7:0] Longword Line 20.6 External Bus Interface Types The MCF5272 supports three types of external bus interfaces. The interface type is programmed using CSBRn[EBI].
Page 463 External Bus Interface Types CLKIN A[22:0] D[31:0] OE, BS[3:0] Figure 20-3. Longword Read; EBI = 00; 32-Bit Port; Internal Termination NOTE: Wait states, if needed, are added immediately after C2 in Figure 20-3. Chapter 20. Bus Operation 20-11...
Page 464 External Bus Interface Types CLKIN A[22:0] D[31:0] BS[1:0] BS[3:2] Figure 20-4. Word Write; EBI = 00; 16-/32-Bit Port; Internal Termination CLKIN A[22:0] D[31:0] OE, BS[3:0] Figure 20-5. Longword Read with Address Setup; EBI = 00; 32-Bit Port; Internal Termination 20-12 MCF5272 User’s Manual...
Page 465 External Bus Interface Types CLKIN A[22:0] D[31:0] BS[3:0] Figure 20-6. Longword Write with Address Setup; EBI = 00; 32-Bit Port; Internal Termination CLKIN A[22:0] D[31:0] OE, BS[3:0] Figure 20-7. Longword Read with Address Hold; EBI = 00; 32-Bit Port; Internal Termination Chapter 20.
Page 466 External Bus Interface Types CLKIN A[22:0] D[31:0] BS[3:0] Figure 20-8. Longword Write with Address Hold; EBI = 00; 32-Bit Port; Internal Termination CLKIN A[22:0] D[31:0] BS[3:0] Figure 20-9. Longword Read; EBI = 00; 32-Bit Port; Terminated by TA with One Wait State 20-14 MCF5272 User’s Manual...
Page 467: Interface For Flash/Sram Devices Without Byte Strobes
External Bus Interface Types 20.6.2 Interface for FLASH/SRAM Devices without Byte Strobes CSBRn[EBI] is 11 for FLASH/SRAM devices and for peripherals having 8-bit data bus widths and no byte strobe inputs. These type of memory devices have separate pins for write enable, chip select, and output enable.
Page 468 External Bus Interface Types CLKIN A[22:0] D[31:0] BS[1:0] BS[3:2] Figure 20-11. Word Write; EBI=11; 16/32-Bit Port; Internal Termination 20-16 MCF5272 User’s Manual...
Page 469 External Bus Interface Types CLKIN A[22:0] D[31:0] BS[3:0] Figure 20-12. Read with Address Setup; EBI=11; 32-Bit Port; Internal Termination CLKIN A[22:0] D[31:0] BS[3:0] Figure 20-13. Longword Write with Address Setup; EBI=11; 32-Bit Port; Internal Termination Chapter 20. Bus Operation 20-17...
Page 470 External Bus Interface Types CLKIN A[22:0] D[31:0] BS[3:0] Figure 20-14. Read with Address Hold; EBI=11; 32-Bit Port; Internal Termination CLKIN A[22:0] D[31:0] BS[3:0] Figure 20-15. Longword Write with Address Hold; EBI=11; 32-Bit Port; Internal Termination 20-18 MCF5272 User’s Manual...
Page 471 External Bus Interface Types CLKIN A[22:0] D[31:0] BS[3:0] Figure 20-16. Longword Read with Address Setup and Address Hold; EBI = 11; 32-Bit Port, Internal Termination CLKIN A[22:0] D[31:0] BS[3:0] Figure 20-17. Longword Write with Address Setup and Address Hold; EBI = 11; 32-Bit Port, Internal Termination Chapter 20.
Page 472: Burst Data Transfers
Burst Data Transfers 20.7 Burst Data Transfers The MCF5272 uses line read transfers to access 16 bytes to support cache line ﬁllingDMA transfers, and MOVEM instructions, when appropriate. A cache line read accesses a block of four longwords, aligned to a longword memory boundary, by supplying a starting address that points to one of the longwords and incrementing A[3:0] of the supplied address for each transfer.
Page 473: Interrupt Cycles
Interrupt Cycles longword is misaligned at an address that is not evenly divisible by four. However, because operands can reside at any byte boundary, they can be misaligned. Although the MCF5272 does not enforce any alignment restrictions for data operands (including program counter (PC) relative data addressing), signiﬁcant performance degradation can occur when additional bus cycles are required for longword or word operands that are misaligned.
Page 474: Bus Errors
Bus Errors dedicated to an external peripheral. It is possible to have multiple external peripherals share an INTx pin but software must then determine which peripheral caused the interrupt. The interrupt priority level and the signal level of each interrupt pin are individually programmable.
Page 475 Bus Errors CLKIN A[22:0] D[31:0] BS[3:0] Figure 20-20. Longword Write Access To 32-Bit Port Terminated with TEA Timing Clock 1 (C1) The write cycle starts in C1. During C1, the MCF5272 places valid values on the address bus (A[22:0]) and the chip select signal. Clock 2 (C2) During C2, the MCF5272 drives the data bus, the byte strobes, and R/W.
Page 476: Bus Arbitration
Bus Arbitration NOTE: TEA normally should be asserted for no more than three CLKIN periods. The minimum is two clock periods. NOTE: TEA is internally synchronized on the rising edge of CLKIN. Depending on when this synchronization takes place, the Cx cycle may not occur.
Page 477: Master Reset
Reset Operation NOTE: Master reset must be asserted for all power-on resets. This is done by driving RSTI and DRESETEN low simultaneously. Failure to assert master reset during power-on sequences results in unpredictable DRAM controller behavior. 20.12.1 Master Reset To perform a master reset, an external device asserts RSTI and DRESETEN simultaneously for a minimum of six CLKIN cycles after VDD is within tolerance.
Page 478: Normal Reset
Reset Operation The levels of the mode select inputs, QSPI_Dout/WSEL, QSPI_CLK/BUSW1, and QSPI_CS0/BUSW0, are sampled when RSTI negates and select the port size of CS0 and the physical data bus width after a master reset occurs. The INTx signals are synchronized and are registered on the last falling edge of CLKIN where RSTI is asserted.
Page 479: Software Watchdog Timer Reset Operation
Reset Operation QSPI_CS0/BUSW0, are sampled when RSTI negates and select the port size of CS0 and the physical data bus width after a master reset occurs. The INTx signals are synchronized and are registered on the last falling edge of CLKIN where RSTI is asserted. During the normal reset period, all outputs are driven to their default levels.
Page 480: Soft Reset Operation
Reset Operation During the software watchdog timer reset period, all outputs are driven to their default levels. Once RSTO negates, all bus signals continue to remain in this state until the ColdFire core begins the ﬁrst bus cycle for reset exception processing. During a software watchdog timer reset, SCE[RSTSRC] is set to 0b10 to indicate the software watchdog as the source of the previous reset.
Page 481 Reset Operation NOTE: Like the normal reset, the soft reset does not reset the SDRAM controller unless DRESETEN is asserted during the reset. When DRESETEN is negated, SDRAM refreshes continue to be generated during and after reset at the programmed rate and with the programmed waveform timing.
Page 482 Reset Operation 20-30 MCF5272 User’s Manual...
Page 483: Ieee 1149.1 Test Access Port (Jtag)
TDO changes on the falling edge of TCK. These signals, described in detail in Table 21-1, are enabled by negating the Motorola test mode signal (MTMOD). TRST is not provided because TAP pins are reset by an internal power-on reset circuit.
Page 484: Jtag Test Access Port And Bdm Debug Port
JTAG Test Access Port and BDM Debug Port The MCF5272 implementation can do the following: • Perform boundary scan operations to test circuit board electrical continuity • Sample MCF5272 system pins during operation and transparently shift out the result in the boundary scan register •...
Page 485: Tap Controller
JTAG test reset. TRST asynchronously resets the JTAG TAP logic when low. DSCLK MTMOD Motorola test mode select. Negating MTMOD enables JTAG mode; asserting it enables BDM mode. 21.3 TAP Controller The TAP controller is a synchronous state machine that controls JTAG logic and interprets the sequence of logical values on TMS.
Page 486: Boundary Scan Register
Boundary Scan Register TEST LOGIC RESET SELECT-DR_SCAN SELECT-IR_SCAN RUN-TEST/IDLE CAPTURE-IR CAPTURE-DR SHIFT-IR SHIFT-DR EXIT1-IR EXIT1-DR PAUSE-IR PAUSE-DR EXIT2-IR EXIT2-DR UPDATE -IR UPDATE-DR Figure 21-2. TAP Controller State Machine 21.4 Boundary Scan Register The boundary scan register contains bits for all device signal and clock pins and associated control signals.
Page 487 Boundary Scan Register Figure 21-3 to Figure 21-8 show the four MCF5272 cell types. 1 = EXTEST, CLAMP, HI-Z To next Shift DR 0 = Otherwise cell Data from system To output logic buffer From last cell Clock DR Update DR Figure 21-3.
Page 488 Boundary Scan Register 1 = EXTEST, CLAMP, HI-Z To next Shift DR 0 = Otherwise cell 0 = HI-Z 1 = Otherwise To output Output control buffer from system logic I/O direction From last cell Clock DR Update DR Figure 21-5. Output Control Cell (En.Cell) (BC–4) 1 = EXTEST, CLAMP, HI-Z 0 = Otherwise 1 = Output...
Page 489: Instruction Register
Instruction Register TO NEXT CELL OUTPUT EN.CELL ENABLE OUTPUT DIRECTION ENABLE OUTPUT DATA IO.CELL INPUT DATA FROM LAST CELL NOTE: More than one lO.Cell could be serially connected and controlled by a single En.Cell. Figure 21-7. General Arrangement for Bidirectional Pins 21.5 Instruction Register The MCF5272 IEEE 1149.1 implementation includes the three mandatory public instructions (EXTEST, SAMPLE/PRELOAD, and BYPASS), the optional public ID...
Page 490: Restrictions
Restrictions Table 21-2. Instructions (Continued) B[3:0] Instruction Description 0010 SAMPLE/ The SAMPLE/PRELOAD instruction selects the boundary scan register and provides two PRELOAD separate functions. First, it provides a means to obtain a snapshot of system data and control signals. The snapshot occurs on the rising edge of TCK in the capture-DR controller state.
Page 491: Non-Ieee 1149.1 Operation
Non-IEEE 1149.1 Operation 21.7 Non-IEEE 1149.1 Operation In non-IEEE 1149.1 operation, IEEE 1149.1 test logic must be made transparent to system logic by forcing the TAP controller into test-logic-reset state, which takes at least ﬁve consecutive TCK rising edges with TMS high. TMS has an internal pull-up resistor and may be left unconnected.
Page 492 Non-IEEE 1149.1 Operation 21-10 MCF5272 User’s Manual...
Page 493: Mechanical Data
Chapter 22 Mechanical Data This chapter contains drawings showing the pinout and the packaging and mechanical characteristics of the MCF5272. 22.1 Pinout Figure 22-1 shows a pinout of the MCF5272. DDATA DDATA SDCS DDATA MTMOD SDWE BKPT DDATA PSTCLK TRST SDCLKE PRECHG DSCLK...
Page 494: Package Dimensions
Package Dimensions 22.2 Package Dimensions Figure 22-2 shows MCF5272 package dimensions. NOTES: 1. Dimensions are in millimeters. 2. Interpret dimensions and tolerances Laser mark for pin 1 per ASME Y14.5M, 1994. identification in this area 3. Dimension B is measured at the maximum solder ball diameter, parallel to datum plane Z.
Page 495: Electrical Characteristics
Motorola’s ColdFire page, http://www.motorola.com/coldﬁre, to conﬁrm that this is the latest information. 23.1 Maximum Ratings Maximum ratings are here supplied. 23.1.1 Supply, Input Voltage, and Storage Temperature Table 23-1 lists maximum voltages and temperatures. Table 23-1. Maximum Supply, Input Voltage and Storage Temperature...
Page 496: Resistance
Ψ parameters are simulated in accordance with EIA/JESD Standard 51-2 for natural convection. Motorola recommends the use of θ and power dissipation specifications in the system design to prevent device junction temperatures from exceeding the rated specification. System designers should be aware that device junction temperatures can be significantly influenced by board layout and surrounding devices.
Page 497: Output Driver Capability And Loading
DC Electrical Speciﬁcations Table 23-4. DC Electrical Specifications (Continued) Characteristic Symbol Unit Input leakage current @ GND, V CLKIN, D[31:0], PA[15:0], PB[15:0], — µA TIN[1:0], DRQ, CLK, TEA, PST[3:0], DDATA[3:0], RSTI, DRESETEN, TDI, TCK, HIZ, MTMOD HI-Z (three-state) leakage current @GND, V , A[22:0], D[31:0], OE/RD, —...
Page 498 AC Electrical Speciﬁcations Table 23-5. I/O Driver Capability (Continued) Signal Drive Capability Output Load (C RSTO 4 mA 30 pF PA[13:0] 2 mA 30 pF PA14 4 mA 30 pF PA15_INT6 2 mA 30 pF PB0,PB3,PB7 4 mA 30 pF PB[2:1],PB[6:4] 2 mA 30 pF...
Page 499: Clock Input And Output Timing Specifications
AC Electrical Speciﬁcations AC timing speciﬁcations referenced to SDCLK assume SDRAM control register bit 3 is 0. After reset this bit is set. 23.3.1 Clock Input and Output Timing Speciﬁcations Table 23-6 lists clock input and output timings. Table 23-6. Clock Input and Output Timing Specifications 0–66 MHz Name Characteristic...
Page 500: Processor Bus Input Timing Specifications
AC Electrical Speciﬁcations Table 23-7. Processor Bus Input Timing Specifications 0–66 MHz Name Characteristic Unit Min Max Control Inputs RSTI valid to SDCLK (setup) — TA valid to SDCLK (setup) — TEA valid to SDCLK (setup) — INTx valid to SDCLK (setup) —...
Page 501 AC Electrical Speciﬁcations * The timings are also valid for inputs sampled on the negative clock edge. 1.5V SDCLK Output SETUP HOLD Invalid 1.5V Valid 1.5V Invalid Input Setup And Hold = 1.5 nS rise Input Rise Time = 1.5 nS fall Input Fall Time SDCLK...
Page 502: Processor Bus Output Timing Specifications
AC Electrical Speciﬁcations Table 23-8. Processor Bus Output Timing Specifications 0–66 MHz Name Characteristic Unit Control Outputs SDCLK to chip selects (CS[6:0]) valid — SDCLK to byte enables (BS[3:0]) valid — SDCLK to output enable (OE) valid — SDCLK to write enable (R/W) valid —...
Page 503 AC Electrical Speciﬁcations SDCLK A[22:0] BS[3:0] D[31:0] TEA (H) Figure 23-3. Read/Write SRAM Bus Timing Figure 23-4 shows an SRAM bus cycle terminated by TA showing timings listed in Table 23-8. Chapter 23. Electrical Characteristics 23-9 PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 504 AC Electrical Speciﬁcations SDCLK A[22:0] BS[3:0] D[31:0] Figure 23-4. SRAM Bus Cycle Terminated by TA Figure 23-5 shows an SRAM bus cycle terminated by TEA showing timings listed in Table 23-8. 23-10 MCF5272 User’s Manual PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 505 AC Electrical Speciﬁcations SDCLK A[22:0] BS[3:0] D[31:0] Figure 23-5. SRAM Bus Cycle Terminated by TEA Figure 23-6 shows reset and mode Select/HIZ conﬁguration timing showing parameters listed in Table 23-8. SDCLK Reset is asynchronous. Assert for at least 2 RSTI consecutive SDCLK rising edges Mode selects...
Page 506: Debug Ac Timing Specifications
Debug AC Timing Speciﬁcations 23.4 Debug AC Timing Speciﬁcations Table 23-9 lists speciﬁcations for the debug AC timing parameters shown in Figure 23-8. Table 23-9. Debug AC Timing Specification 0-66 MHz Characteristic Units PST[3:0], DDATA[3:0] to PSTCLK valid — PSTCLK to PST[3:0], DDATA[3:0] hold —...
Page 507: Sdram Interface Timing Specifications
Debug AC Timing Speciﬁcations 23.4.1 SDRAM Interface Timing Speciﬁcations Table 23-10 lists SDRAM interface timings. Table 23-10. SDRAM Interface Timing Specifications 0–66 MHz Name Characteristic Unit Control Inputs SDCLK to address output A[22:0] valid — SDCLK to address output A[22:0] invalid (output hold) —...
Page 508 Debug AC Timing Speciﬁcations SDCLK SDADR[13:0] SD11 A10_PRECHG SD12 SDBA[1:0] SDCS SD10 RAS0 CAS0 SDCLKE SDWE DQMx SD14 DATA IN (READ SDCR (b4=1)) SD16 SD15 DATA IN (READ SDCR (b4=0)) SD16 SD13 DATA OUT (WRITE) Figure 23-9. SDRAM Signal Timing 23-14 MCF5272 User’s Manual PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 509: Mii Receive Signal Timing (E_Rxd[3:0], E_Rxdv, E_Rxer And E_Rxclk)
Debug AC Timing Speciﬁcations Figure 23-10 shows SDRAM self-refresh timings listed in Table 23-10. SDCLK SDWE RAS0 CAS0 Figure 23-10. SDRAM Self-Refresh Cycle Timing 23.4.2 Fast Ethernet AC Timing Speciﬁcations MII signals use TTL signal levels compatible with devices operating at either 5.0 V or 3.3 V. 23.4.2.1 MII Receive Signal Timing (E_RxD[3:0], E_RxDV, E_RxER, and E_RxCLK) The receiver functions correctly up to a E_RxCLK maximum frequency of 25 MHz +1%.
Page 510: Mii Transmit Signal Timing (E_Txd[3:0], E_Txen, E_Txer E_Txclk)
Debug AC Timing Speciﬁcations E_RxCLK (input) E_RxD[3:0] (inputs) E_RxDV E_RxER Figure 23-11. MII Receive Signal Timing Diagram 23.4.2.2 MII Transmit Signal Timing (E_TxD[3:0], E_TxEN, E_TxER, E_TxCLK) Table 23-12 lists MII transmit channel timings. The transmitter functions correctly up to a E_TxCLK maximum frequency of 25 MHz +1%.
Page 511: Mii Async Inputs Signal Timing (Crs And Col)
Debug AC Timing Speciﬁcations E_TxCLK (input) E_TxD[3:0] (outputs) E_TxEN E_TxER Figure 23-12. MII Transmit Signal Timing Diagram 23.4.2.3 MII Async Inputs Signal Timing (CRS and COL) Table 23-13 lists MII asynchronous inputs signal timing. Table 23-13. MII Async Inputs Signal Timing Characteristic Unit E_CRS, E_COL minimum pulse width...
Page 512: Timer Module Ac Timing Specifications
Debug AC Timing Speciﬁcations MDC (output) MDIO (output) MDIO (input) Figure 23-14. MII Serial Management Channel Timing Diagram 23.4.3 Timer Module AC Timing Speciﬁcations Table 23-15 lists timer module AC timings. Table 23-15. Timer Module AC Timing Specifications 0–66 MHz Name Characteristic Unit...
Page 513: Uart Modules Ac Timing Specifications
Debug AC Timing Speciﬁcations SDCLK TIN1 IN (Capture Mode Synchronization) TIN1 IN (Clock Mode) Figure 23-15. Timer Timing 23.4.4 UART Modules AC Timing Speciﬁcations Table 23-16 lists UART AC timings. Table 23-16. UART Modules AC Timing Specifications 0–66 MHz Name Characteristic Unit URTnRxD valid to SDCLK (setup)
Page 514 Debug AC Timing Speciﬁcations SDCLK URTn_RxD URTn_CTS URTn_TxD URTn_RTS Figure 23-16. UART Timing 23-20 MCF5272 User’s Manual PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 515 Debug AC Timing Speciﬁcations 23.4.5 PLIC Module: IDL and GCI Interface Timing Speciﬁcations Table 23-17 shows timing for IDL master mode, PLIC ports 1, 2, and 3. Table 23-17. IDL Master Mode Timing, PLIC Ports 1, 2, and 3 Name Characteristic Unit 1, 2...
Page 516 Debug AC Timing Speciﬁcations Table 23-18 lists timing for IDL slave mode. Table 23-18. IDL Slave Mode Timing, PLIC Ports 0–3 Name Characteristic Min Typ Unit FSR0, FSR1 period — — µs P15a FSR0 or FSC0 valid before the falling edge of DCL0 (setup time) —...
Page 517 Debug AC Timing Speciﬁcations FSR[0,1] DOUT[0,1,3] DCL[0:1] DFS[2:3] DIN[0:3] Figure 23-18. IDL Slave Timing Table 23-19 lists timings for GCI slave mode. Table 23-19. GCI Slave Mode Timing, PLIC Ports 0–3 Name Characteristic Unit FSC input high before the falling edge of DCL0, DCL1 (setup time) —...
Page 518 Debug AC Timing Speciﬁcations Table 23-19. GCI Slave Mode Timing, PLIC Ports 0–3 (Continued) Name Characteristic Unit Data valid on DIN0 before rising edge of DCL0, — Data valid on DIN1 or DIN3 before rising edge of DCL1 Data valid on DIN0 after rising edge of DCL0, —...
Page 519 Debug AC Timing Speciﬁcations Table 23-20. GCI Master Mode Timing, PLIC PORTs 1, 2, 3 Name Characteristic Unit Name Delay from rising edge of GDCL1_OUT to Low-Z and valid data on — — DOUT[1,3] Delay from rising edge of GDCL1_OUT to data valid on DOUT[1,3] —...
Page 520: General-Purpose I/O Port Ac Timing Specifications
Debug AC Timing Speciﬁcations Table 23-21. General-Purpose I/O Port AC Timing Specifications 0–66 MHz Name Characteristic Unit PORTx input setup time to SDCLK (rising) — PORTx input hold time from SDCLK (rising) — SDCLK to PORTx output valid — SDCLK to PORTx output invalid (output hold) —...
Page 521: Ieee 1149.1 (Jtag) Ac Timing Specifications
Debug AC Timing Speciﬁcations NOTE: USB signals are sampled; setup and hold times are not normally required in a transceiver connection. Figure 23-22 shows USB timings listed in Table 23-22. USB_CLK (input) US4b US4a USB_RP USB_RN USB_RxD USB_TP USB_TN USB_SUSP USB_TxEN Figure 23-22.
Page 522 Debug AC Timing Speciﬁcations Table 23-23. IEEE 1149.1 (JTAG) AC Timing Specifications (Continued) TCK falling edge to boundary scan data valid (signal from driven or three-state) — TCK falling edge to boundary scan data high impedance — Figure 23-23 shows JTAG timings listed in Table 23-23. TDI, TMS Boundary Scan Data...
Page 523 Debug AC Timing Speciﬁcations Table 23-24. QSPI Modules AC Timing Specifications (Continued) 0–66 MHz Name Characteristic Unit QS10 QSPI_DIN to SDCLK high. (Input setup) — QS11 QSPI_CLK to QSPI_DIN invalid. (Input hold) — QS12 SDCLK to QSPI_DIN invalid. (Input hold) —...
Page 524 Debug AC Timing Speciﬁcations The values in Table 23-25 correspond to Figure 23-25. SDCLK PWM_OUT[2:0] Figure 23-25. PWM Timing 23-30 MCF5272 User’s Manual PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 525: Overview
Appendix A List of Memory Maps A.1 Overview The MCF5272 memory map is given in this section. The addresses for the system conﬁguration registers are absolute addresses in the MCF5272 CPU space memory map. The on-chip peripheral modules are conﬁgured as a group by programming the module base address register, (MBAR).
Page 526 List of Memory Map Tables Table A-1. On-Chip Module Base Address Offsets from MBAR Module Base Module Mnemonic Address Ethernet Module Registers MBAR+0x0800 ENET_Base USB Module Registers MBAR+0x1000 USB_Base Table A-2. CPU Space Registers Memory Map SYSTEM CONFIGURATION SPACE NAME Size Program Access Debug Access...
Page 527 List of Memory Map Tables Table A-4. Interrupt Control Register Memory Map MBAR [31:24] [23:16] [15:8] [7:0] Offset 0x0020 Interrupt Control Register 1 (ICR1) 0x0024 Interrupt Control Register 2 (ICR2) 0x0028 Interrupt Control Register 3 (ICR3) 0x002C Interrupt Control Register 4 (ICR4) 0x0030 Interrupt Source Register (ISR) 0x0034...
Page 528 List of Memory Map Tables Table A-6. GPIO Port Register Memory Map MBAR [31:24] [23:16] [15:8] [7:0] Offset 0x0088 Port B Control Register (PBCNT) 0x008C Port B Data Direction Register (PBDDR) Reserved 0x008E Reserved Port B Data Register (PBDAT) 0x0094 Port C Data Direction Register (PCDDR) Reserved 0x0096...
Page 529 List of Memory Map Tables Table A-9. DMA Module Memory Map (Continued) MBAR [31:24] [23:16] [15:8] [7:0] Offset 0x00E8 DMA Byte Count Register (DBCR) 0x00EC DMA Source Address Register (DSAR) 0x00F0 DMA Destination Address Register (DDAR) Table A-10. UART0 Module Memory Map MBAR [31:24] [23:16]...
Page 530 List of Memory Map Tables Table A-10. UART0 Module Memory Map (Continued) MBAR [31:24] [23:16] [15:8] [7:0] Offset 0x0138 UART0 RTS O/P Bit Set Reserved Command Register (U0OP1) 0x013C UART0 RTS O/P Bit Reserved Reset Command Register (U0OP0) Table A-11. UART1 Module Memory Map MBAR [31:24] [23:16]...
Page 531 List of Memory Map Tables Table A-11. UART1 Module Memory Map (Continued) MBAR [31:24] [23:16] [15:8] [7:0] Offset 0x0174 UART1 CTS Unlatched Reserved Input (U1IP) 0x0178 UART1 RTS O/P Bit Set Reserved Command Register (U1OP1) 0x017C UART1 RTS O/P Bit Reserved Reset Command Register (U1OP0)
Page 532 List of Memory Map Tables Table A-13. Timer Module Memory Map (Continued) MBAR [31:24] [23:16] [15:8] [7:0] Offset 0x0270 Timer 3 Event Register (TER3) Reserved 0x0280 Watchdog Reset Reference Register (WRRR) Reserved 0x0284 Watchdog Interrupt Reference Register (WIRR) Reserved 0x0288 Watchdog Counter Register (WCR) Reserved 0x028C...
Page 533 List of Memory Map Tables Table A-14. PLIC Module Memory Map (Continued) MBAR [31:24] [23:16] [15:8] [7:0] Offset 0x0364 Port2 GCI Monitor RX (P2GMR) Port3 GCI Monitor RX (P3GMR) 0x0368 Port0 GCI Monitor TX (P0GMT) Port1 GCI Monitor TX (P1GMT) 0x036C Port2 GCI Monitor TX (P2GMT) Port3 GCI Monitor TX (P3GMT)
Page 534 List of Memory Map Tables Table A-15. Ethernet Module Memory Map MBAR [31:24] [23:16] [15:8] [7:0] Offset 0x0984 Ethernet Tx Control Register (TCR) 0x0C00 Ethernet Address (Lower) (MALR) 0x0C04 Ethernet Address (Upper) (MAUR) 0x0C08 Ethernet Hash Table (Upper) (HTUR) 0x0C0C Ethernet Hash Table (Lower) (HTLR) 0x0C10 Ethernet Rx Descriptor Ring (ERDSR)
Page 535 List of Memory Map Tables Table A-16. USB Module Memory Map (Continued) MBAR [31:24] [23:16] [15:8] [7:0] Offset 0x1050 Reserved USB Endpoint 1 Control Register (EP1CTL) 0x1054 Reserved USB Endpoint 2 Control Register (EP2CTL) 0x1058 Reserved USB Endpoint 3 Control Register (EP3CTL) 0x105C Reserved USB Endpoint 4 Control Register (EP4CTL)
Page 536 List of Memory Map Tables Table A-16. USB Module Memory Map (Continued) MBAR [31:24] [23:16] [15:8] [7:0] Offset 0x10DC Reserved USB Endpoint 4 Data Present Register (EP4DPR) 0x10E0 Reserved USB Endpoint 5 Data Present Register (EP5DPR) 0x10E4 Reserved USB Endpoint 6 Data Present Register (EP6DPR) 0x10E8 Reserved USB Endpoint 7 Data Present Register (EP7DPR)
Page 537 Appendix B Buffering and Impedance Matching When required: • SDRAM and a large number of external peripherals are required for a particular system conﬁguration. • Some peripherals may have excessive input capacitance. • Minimize signal reﬂections at higher clock speeds. •...
Page 538 74LVC245 Signal = BS[3:0] = Ax:A2 (32 bit bus) = Ax:A1 (16 bit bus) = Resistor Arrays 10-75 ohms RA1, RA2, RA3, ... R1, R2, ... = resistor 10-75 ohms B[7:0] A[7:0] D31:D0 Signals M CF5272 SDRAM Flash Device Device Device Figure B-1.
Page 539: Coldfire Core
INDEX Access control register, 4-15 Cache ACR0 and ACR1, 4-15 configuration register, 2-19 Activate low-power register, 6-10 registers, access control, 2-20 Address bus, 20-2 Cache control register, 4-13 Address variant, 5-5 Caches Addressing coherency and validation, 4-9 mode summary, 2-22 miss fetch algorithm/line fills, 4-11 Addressing mode summary, 2-22 CAM interface, 11-6...
Page 540 INDEX module enhancements, 2-14 FIFO real-time support, 5-37 receive bound register, 11-20 taken branch, 5-4 receive start register, 11-20 theory, 5-38 transmit start register, 11-22 Device identification register, 6-11 frame reception, 11-5 address modes, 10-2 transmission, 11-4 byte count register, 10-6 hardware initialization, 11-31 controller registers, 10-2 hash table...
Page 541 INDEX restrictions, 21-8 TAP controller, 21-3 GPIO test access port, 21-2 overview, 17-1 port control registers, 17-2, 17-8 data direction registers, 17-10 Local memory data registers, 17-11 module interactions, 4-1 registers, 4-2 Loopback, Ethernet internal and external, 11-9 Halt, fault-on-fault, 5-16 Hardware Ethernet initialization, 11-31 Hash table...
Page 542 INDEX receive registers, 13-29 transmit registers, 13-31 Parallel input/output ports, 1-6 transmit status register, 13-31 Pin descriptions, ??–19-37 GCI interrupts aperiodic status, 13-11 address bus, 19-16 GCI monitor channel byte strobes, 19-17 receive registers, 13-26 clock, 19-23 transmit abort register, 13-28 data bus, 19-16 transmit registers, 13-27 dynamic data bus sizing, 19-17...
Page 543 INDEX PULSE instruction, 5-4 ALPR, 6-10 B2 data transmit, 13-19 control register, 18-3 BI data receive, 13-16 operation, 18-2 cache configuration, 2-19 overview, 18-1 cache control, 4-13 programming model, 18-2 CACR, 2-19 width register, 18-4 CCR, 2-17 chip select base, 8-3 general, 8-2 QSPI option, 8-5...
Page 544 INDEX event, 11-13 transmit, 13-27 mask, 11-14 transmit status, 13-28 vector status, 11-14 general, 13-16 interrupt controller interrupt configuration, 13-22 pending and mask, 7-5, 7-6 loopback control, 13-21 interrupt controller, pending and mask, 7-4, 7-5 memory map, 13-15 periodic status, 13-24 JTAG instruction, 21-7 local memory, 4-2 port configuration, 13-20...
Page 545 INDEX TCR, 15-5 overview, 4-5 TDR, 5-13 programming model, 4-6 TER, 15-5 ROMBAR timer overview, 4-6 capture, 15-5 power management programming, 4-7 event, 15-5 general-purpose, 15-3 mode, 15-3 SDCR, 9-13 reference, 15-4 SDRAM TMR, 15-3 auto initialization, 9-10 transmit banks, page hits, page misses, 9-6 control, 11-25 configuration register, 9-7 descriptor active, 11-16...
Page 546 INDEX Timings overview, 1-5 SDRAM refresh, 9-21 programming model, 6-3 Transmit signal timing, 23-16 register memory map, 6-3 Software watchdog timer, 6-12 SRAM UART modules base address register, 4-3 bus operation initialization, 4-4 interrupt acknowledge cycles, 16-31 overview and operation, 4-2 read cycles, 16-31 programming model, 4-2 write cycles, 16-31...
Page 547 INDEX frame number match register, 12-9 function address register, 12-11 IN endpoints, 12-32, 12-33 initialization, 12-30 isochronous endpoints, 12-33 line interface, 12-35 memory map, 12-7 module operation, 12-3 OUT endpoints, 12-32, 12-33 overview, 12-1 PCB layout recommendations, 12-36 register access, 12-29 descriptions, 12-9, 12-27 remote wakeup and resume operation, 12-34 request processor, 12-5...
Page 548 INDEX Index-12 MCF5272 User’s Manual...
Page 549: Hardware Multiply/Accumulate (Mac) Unit
Overview ColdFire Core Hardware Multiply/Accumulate (MAC) Unit Local Memory Debug Support System Integration Module (SIM) Interrupt Controller Chip-Select Module SDRAM Controller DMA Controller Module Ethernet Module Universal Serial Bus (USB) Physical Layer Interface Controller (PLIC) Queued Serial Peripheral Interface (QSPI) Module Timer Module UART Modules General-Purpose I/O Module...
Page 550: Local Memory
Overview ColdFire Core Hardware Multiply/Accumulate (MAC) Unit Local Memory Debug Support System Integration Module (SIM) Interrupt Controller Chip-Select Module SDRAM Controller DMA Controller Module Ethernet Module Universal Serial Bus (USB) Physical Layer Interface Controller (PLIC) Queued Serial Peripheral Interface (QSPI) Module Timer Module UART Modules General-Purpose I/O Module...

Motorola DigitalDNA ColdFire MCF5272 User Manual

Chapter 1 Overview

Chapter 2 Coldfire Core

Chapter 3

Chapter 4 Local Memory

Chapter 5 Debug Support

Chapter 7 Interrupt Controller

Chapter 9

Chapter 8

Chapter 10

Chapter 11

Chapter 12

Chapter 13

Chapter 14 Queued Serial Peripheral Interface (QSPI) Module

Chapter 15

Chapter 17 Port Control Registers

Chapter 16

Chapter 18 PWM Operation

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Summary of Contents for Motorola DigitalDNA ColdFire MCF5272