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Programming Model
14.4.9
UART 2 Baud Control Register
The UART 2 baud control (UBAUD2) register controls the operation of the baud rate generator, the
integer prescaler, and the UCLK signal. The bit position assignments for this register are shown in the
following register display. The settings for this register are described in Table 14-11.
UBAUD2
BIT 15
14
TYPE
0
0
RESET
Table 14-11. UART 2 Baud Control Register Description
Name
Reserved
Reserved
Bits 15–14
UCLKDIR
UCLK Direction—This bit controls the
Bit 13
direction of the UCLK signal. When this bit
is low, the signal is an input, and when it is
high, it is an output. However, the SELx bit
in the Port E registers must be 0. See
Section 10.4.6, "Port E Registers," on
page 10-21 for more information.
Reserved
Reserved
Bit 12
BAUD SRC
Baud Source—This bit controls the clock
Bit 11
source to the baud rate generator.
DIVIDE
Divide—These bits control the clock fre-
Bits 10–8
quency produced by the baud rate genera-
tor.
Reserved
Reserved
Bits 7–6
PRESCALER
Prescaler—These bits control the division
Bits 5–0
value of the baud generator prescaler. The
division value is determined by the follow-
ing formula:
Prescaler division value =
65 (decimal) – PRESCALER
14-22
UART 2 Baud Control Register
13
12
11
UCLK
BAUD
DIR
SRC
rw
rw
0
0
0
Description
MC68VZ328 User's Manual
10
9
8
7
6
5
DIVIDE
rw
rw
rw
rw
0
0
0
0
0
1
0x003F
These bits are reserved and should be set to 0.
0 = UCLK is an input.
1 = UCLK is an output.
This bit is reserved and should be set to 0.
0 = Baud rate generator source is from system
clock.
1 = Baud rate generator source is from UCLK pin
(UCLKDIR must be set to 0).
000 = Divide by 1.
001 = Divide by 2.
010 = Divide by 4.
011 = Divide by 8.
100 = Divide by 16.
101 = Divide by 32.
110 = Divide by 64.
111 = Divide by 128.
These bits are reserved and should be set to 0.
See description.
0x(FF)FFF912
4
3
2
1
BIT 0
PRESCALER
rw
rw
rw
rw
rw
1
1
1
1
1
Setting
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