Lcd Dram Dma Cycle 16-Bit Fast Page Mode Access (Lcd Bus Master); Figure 19-12 Lcd Dram Dma Cycle 16-Bit Fast Page Mode Access (Lcd Bus Master); Table 19-14 Lcd Dram Dma Cycle 16-Bit Fast Page Mode Access (Lcd Bus Master) - Motorola MC68VZ328 User Manual

AC Electrical Characteristics
19.3.12 LCD DRAM DMA Cycle 16-Bit Fast Page Mode Access
(LCD Bus Master)
Figure 19-12 shows the timing diagram for the LCD DRAM DMA cycle for 16-bit Fast Page Mode mode
access (LCD bus master). The signal values and units of measure for this figure are found in Table 19-14.
Detailed information about the operation of individual signals can be found in Chapter 7, "DRAM
Controller," and Chapter 8, "LCD Controller."
MD[12:0]
RASx
1
CASx
DWE
OE
D[15:0]
Figure 19-12. LCD DRAM DMA Cycle 16-Bit Fast Page Mode Access (LCD Bus Master)
Table 19-14. LCD DRAM DMA Cycle 16-Bit Fast Page Mode Access (LCD Bus Master)
Number
1 Row address valid to RASx asserted
2 DWE negated before row address valid
3 OE asserted before RASx asserted
4 RASx asserted before row address invalid
(MSW = 0,1)
5 Column address valid to CASx asserted
(MSW = 0,1)
6 RASx asserted to CASx asserted (MSW = 0,1)
7 Data setup time
8 CASx asserted before column address invalid
19-16
Row Col 1
4
5
2
6
3
Timing Diagram
Timing Parameters
Characteristic
MC68VZ328 User's Manual
Col 2 Col 3 Col n
8
11
10
9
7
(3.0 ± 0.3) V
Minimum
45
0
0
12,27
10,25
28,58
15
20
Col n+1
12
14
13
Maximum
—
—
—
—
—
—
—
—
Unit
ns
ns
ns
ns
ns
ns
ns
ns