Interrupt Control Register; Table 9-4 Interrupt Control Register Description - Motorola MC68VZ328 User Manual

Programming Model
9.6.2

Interrupt Control Register

The interrupt control register (ICR) controls the behavior of the external interrupt inputs. It informs the
interrupt controller whether the interrupt signal is an edge-triggered or a level-sensitive interrupt, as well as
whether it has positive or negative polarity. The bit assignments for this register are shown in the following
register display, and the settings for the bit positions are listed in Table 9-4.
ICR
BIT 15 14
POL1 POL2
TYPE rw rw
0 0
RESET
Name
POL1 Polarity Control 1—This bit controls interrupt polarity for the IRQ1 signal. In
Bit 15 level-sensitive mode, negative polarity produces an interrupt when the signal is
at logic level low. Positive polarity produces an interrupt when the signal is at
logic level high. In edge-triggered mode, negative polarity produces an interrupt
when the signal goes from logic level high to logic level low. Positive polarity
generates an interrupt when the signal goes from logic level low to logic level
high.
POL2 Polarity Control 2—This bit controls interrupt polarity for the IRQ2 signal. In
Bit 14 level-sensitive mode, negative polarity produces an interrupt when the signal is
at logic level low. Positive polarity produces an interrupt when the signal is at
logic level high. In edge-triggered mode, negative polarity produces an interrupt
when the signal goes from logic level high to logic level low. Positive polarity
generates an interrupt when the signal goes from logic level low to logic level
high.
POL3 Polarity Control 3—This bit controls interrupt polarity for the IRQ3 signal. In
Bit 13 level-sensitive mode, negative polarity produces an interrupt when the signal is
at logic level low. Positive polarity produces an interrupt when the signal is at
logic level high. In edge-triggered mode, negative polarity produces an interrupt
when the signal goes from logic level high to logic level low. Positive polarity
generates an interrupt when the signal goes from logic level low to logic level
high.
POL6 Polarity Control 6—This bit controls interrupt polarity for the IRQ6 signal. In
Bit 12 level-sensitive mode, negative polarity produces an interrupt when the signal is
at logic level low. Positive polarity produces an interrupt when the signal is at
logic level high. In edge-triggered mode, negative polarity produces an interrupt
when the signal goes from logic level high to logic level low. Positive polarity
generates an interrupt when the signal goes from logic level low to logic level
high.
ET1 IRQ1 Edge Trigger Select—When this bit is set, the IRQ1 signal is an
Bit 11 edge-triggered interrupt. In edge-triggered mode, a 1 must be written to the
IRQ1 bit in the interrupt status register to clear this interrupt. When this bit is
low, IRQ1 is a level-sensitive interrupt. In this case, the external source of the
interrupt must be cleared.
9-8
Interrupt Control Register
13 12 11 10
POL3 POL6 ET1 ET2
rw rw rw
0 0 0
Table 9-4. Interrupt Control Register Description
Description
MC68VZ328 User's Manual
9 8 7
ET3 ET6 POL5
rw rw rw rw
0 0 0 0
0x0000
0x(FF)FFF302
6 5 4 3 2 1 BIT 0
0 0 0 0 0 0
Setting
0 = Negative
polarity.
1 = Positive
polarity.
0 = Negative
polarity.
1 = Positive
polarity.
0 = Negative
polarity.
1 = Positive
polarity.
0 = Negative
polarity.
1 = Positive
polarity.
0 = Level-sensitive
interrupt.
1 = Edge-sensitive
interrupt.
0