Pll Frequency Select Register; Introduction To The Power Control Module; Table 4-4 Pll Frequency Select Register Settings - Motorola MC68VZ328 User Manual

Introduction to the Power Control Module

4.4.2

PLL Frequency Select Register

The PLL frequency select register (PLLFSR) controls the two dividers of the dual-modulus counter. It also
contains the write-protect bit for the QC and PC counters and the CLK32 status bit. Although PLLFSR
register can be accessed in bytes, it should always be written as a 16-bit word. The settings for each bit and
field in the register is described in Table 4-4.
PLLFSR
BIT 15 14
CLK32 PROT
TYPE r rw*
0 0
RESET
Name
CLK32 Clock32 Status—This read-only bit indicates
Bit 15 the status of the CLK32 clock signal. The bit
switches with each cycle of the CLK32 clock.
PROT Protect Bit—This bit write protects the QC
Bit 14 and PC fields of the PLLFSR. After this bit is
set by software, the register is write protected
until a reset clears this bit.
Reserved Reserved
Bits 13–12
QC Q Counter—This field contains the Q value
Bits 11–8 that is used by the PLL to produce the
PLLCLK.
PC P Counter—This field contains the P value
Bits 7–0 that is used by the PLL to produce the
PLLCLK.
4.5 Introduction to the Power Control Module
The purpose of the power control module (PCM) is to optimize the power consumption of the FLX68000
CPU by turning the CPU off for a programmed number of clock pulses. The CPU consumes more power
than any component in the MC68VZ328, so to conserve power while the CPU is relatively idle, the PCM
can disable the CPU clock or apply the clock in bursts. When the MC68VZ328 is in one of these
reduced-power modes, it is restored to normal operation by a wake-up event. When this occurs, the clock is
immediately enabled, allowing the CPU to service the request. The DMA controller is not affected by the
PCM having full access to the bus while the CPU is idle, keeping the LCD screen refreshed.
4-10
PLL Frequency Select Register
13 12 11 10
rw rw
0 0 0
*This bit can be set by software but is cleared only by reset.
Table 4-4. PLL Frequency Select Register Settings
Description
MC68VZ328 User's Manual
9 8 7 6
QC
rw rw rw rw
0 1 1 0 1
0x0347
0 = CLK32 low.
1 = CLK32 high.
0 = PLLFSR is not protected.
1 = PLLFSR is write protected.
These bits are reserved and must remain at
their default value.
Field value range is 1 < Q < 14.
Field value range is P > Q + 1.
0x(FF)FFF202
5 4 3 2 1
PC
rw rw rw rw rw
0 0 0 1 1
Setting
BIT 0
rw
1