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10.4.5.2
Port D Data Register
The settings for the PDDATA bit positions are shown in Table 10-18.
PDDATA
BIT 7
TYPE
RESET
Name
Description
Dx
Data—These bits reflect the
Bits 7–0
status of the I/O signal.
The eight PDDATA lines are multiplexed with the INT and IRQ dedicated I/O signals whose assignments
are shown in Table 10-19. Port D signals can be programmed as GPIO when not used for handling external
interrupts.
These bits control or report the data on the pins while the associated SELx bits are high. While the DIRx
bits are high (output), the Dx bits control the pins. While the DIRx bits are low (input), the Dx bits report
the signal driving the pins. The Dx bits can be written at any time. Bits that are configured as inputs will
accept the data, but the data written to each cannot be accessed until the corresponding pin is configured as
an output. The actual value on the pin is reported when these bits are read, regardless of whether they are
configured as input or output.
Table 10-19. Port D Dedicated Function Assignments
Bit
0
1
2
3
4
5
6
7
Port D Data Register
6
5
D7
D6
D5
rw
rw
rw
1
1
1
*Actual bit value depends on external circuits connected to pin.
Table 10-18. Port D Data Register Description
0 = Drives the output signal low when DIRx is set to 1 or the
1 = Drives the output signal high when DIRx is set to 1 or the
GPIO Function
Data bit 4
Data bit 5
Data bit 6
Data bit 7
4
3
D4
D3
rw
rw
1
1
0xFF*
Setting
external signal is low when DIRx is set to 0
external signal is high when DIRx is set to 0
Dedicated I/O Function
I/O Ports
Programming Model
0x(FF)FFF419
2
1
BIT 0
D2
D1
D0
rw
rw
rw
1
1
1
INT0
INT1
INT2
INT3
IRQ1
IRQ2
IRQ3
IRQ6
10-17
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