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13.3.2
SPI 1 Transmit Data Register
This write-only data register is the top of the 8
TxFIFO is not full, even if the XCH bit is set. For example, a user may write to TxFIFO during the SPI
data exchange process. In either master or slave mode, a maximum of 8 data words are loaded. Data
written to this register can be of either 8-bit or 16-bit size. The number of bits to be shifted out of a 16-bit
FIFO element is determined by the bit count setting in the SPI 1 status/control register. The unused MSBs
are discarded and may be written with any value. For example, to transfer 10-bit data, a 16-bit word is
written to the SPITXD register, and the 6 MSBs are treated as "don't care" and will not be shifted out. In
slave mode, if no data is loaded to the TxFIFO, zeros are shifted out serially as the TxD signal. Writes to
this register are ignored while the SPIEN bit in the SPI 1 control/status register is clear. The bit position
assignments for this register are shown in the following register display. The settings for this register are
described in Table 13-2.
SPITXD
BIT 7
TYPE
w
0
RESET
Name
DATA
Data—Top SPI data to be loaded to the 8 × 16 TxFIFO
Bits 7–0
×
SPI 1 Transmit Data Register
6
5
w
w
0
0
Table 13-2. SPI 1 Transmit Data Register Description
Description
Serial Peripheral Interface 1 and 2
16 TxFIFO. Writing to TxFIFO is permitted as long as
4
3
DATA
w
w
0
0
0x00
SPI 1 Programming Model
0x(FF)FFF702
2
1
BIT 0
w
w
0
0
Setting
See description
w
0
13-5
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