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Chapter 14
Universal Asynchronous
Receiver/Transmitter 1 and 2
This chapter describes both UARTs in the DragonBall VZ integrated processor. The two UART ports in
the MC68VZ328 may be used to communicate with external serial devices. UART 1 in the DragonBall VZ
processor is identical to the UART in the DragonBall EZ processor, while UART 2 represents an enhanced
version of UART 1. One of the enhancements in the UART 2 design is an enlarged RxFIFO and TxFIFO
to reduce the number of software interrupts. An improvement to both UARTs is the system clock input
frequency, which is 33.16 MHz, doubling the 16.58 MHz frequency of the MC68EZ328. For the
33.16 MHz system clock, software written for the MC68EZ328 version of the chip is not compatible
unless the divider and prescaler are adjusted accordingly to compensate for the increased clock speed.
Because the two UART modules are nearly identical, the signal nomenclature throughout this chapter uses
an x suffix to represent either 1 or 2. For example, TXDx represents either TXD1 or TXD2 depending on
which UART is being used.
14.1
Introduction to the UARTs
This section describes how data is transported in character blocks using the standard "start-stop" format. It
also discusses how to configure and program the UART modules, which have the following features:
•
Full-duplex operation
•
Flexible 5-wire serial interface
•
Direct "glueless" support of IrDA physical layer protocol
•
Robust receiver data sampling with noise filtering
•
12-byte FIFO for receive, 8-byte FIFO for transmit (UART 1)
•
"Old data" timer on receive FIFO
•
7- and 8-bit operation with optional parity
•
Break generation and detection
•
Baud rate generator
•
Flexible clocking options
•
Standard baud rates of 600 bps to 230.4 kbps with 16x sample clock
•
External 1x clock for high-speed synchronous communication
•
Eight maskable interrupts
•
Low-power idle model
Universal Asynchronous Receiver/Transmitter 1 and 2
14-1
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