Port K Pull-Up/Pull-Down Enable Register; Port K Select Register; Table 10-49 Port K Pull-Up/Pull-Down Enable Register Description; Table 10-50 Port K Select Register Description - Motorola MC68VZ328 User Manual

Programming Model
When bit 0 is set as DATA_READY, it can be used in master mode to signal the SPI master to clock out
data. PWMO2 is an output signal from the PWM 2 module. If this pin is configured as this dedicated
function and PKDIR0 is set to 1, the PWMO2 signal is selected. If PKDIR0 is 0, DATA_READY is
selected. This pin defaults to Port K data bit 0, GPIO input, pulled high.
When selected bit 1 (RW) is connected to the 68000 CPU Read/Write signal, this pin defaults to Port K
bit 1, GPIO input, pulled high.
The remaining bits are involved with bus control. See Section 2.6, "Bus Control Signals," on page 2-6 for
more detailed information.
10.4.10.4

Port K Pull-up/Pull-down Enable Register

The pull-up/pull-down enable register (PKPUEN) controls the pull-up and the pull-down resistors for each
line in Port K. The settings for the PKPUEN register bit positions are shown in Table 10-49.
PKPUEN
BIT 7
PD7
TYPE
RESET
Table 10-49. Port K Pull-up/Pull-down Enable Register Description
Name
PUx Pull-up/Pull-down Enable—These bits enable
Bits 7–0 the pull-up and pull-down resistors on the port.
10.4.10.5

Port K Select Register

The select register (PKSEL) determines if a bit position in the data register (PKDATA) is assigned as a
GPIO or to a dedicated I/O function. The settings for the PKSEL register bit positions are shown in
Table 10-50.
PKSEL
BIT 7
SEL7
TYPE
RESET
Name
SELx Select—These bits select whether the internal chip
Bits 7–0 function or I/O port signals are connected to the pins.
10-36
Port K Pull-up/Pull-down Enable Register
6 5
PD6 PD5
rw rw rw
1 1 1
Description
Port K Select Register
6 5
SEL6 SEL5
rw rw rw
1 1 1
Table 10-50. Port K Select Register Description
Description
MC68VZ328 User's Manual
4 3 2
PD4 PU3 PU2
rw rw rw
1 1 1
0xFF
Setting
0 = Pull-up and pull-down resistors are disabled
1 = Pull-up and pull-down resistors are enabled
4 3 2
SEL4 SEL3 SEL2
rw rw rw
1 1 1
0xFF
0 = The dedicated function pins are connected.
1 = The I/O port function pins are connected.
0x(FF)FFF442
1 BIT 0
PU1 PU0
rw rw
1 1
0x(FF)FFF443
1 BIT 0
SEL1 SEL0
rw rw
1 1
Setting