Timer Compare Registers 1 And 2; Table 12-4 Timer Compare Register Description - Motorola MC68VZ328 User Manual

12.2.3

Timer Compare Registers 1 and 2

Each timer compare (TCMPx) register contains the value that is compared with the counter. A compare
event is generated when the counter matches the value in this register. This register is set to 0xFFFF at
system reset. The settings for the registers are described in Table 12-4.
TCMP1
BIT 15 14
TYPE rw rw
1 1
RESET
TCMP2
BIT 15 14
TYPE rw rw
1 1
RESET
Name
COMPARE Compare Value—Write this field's value to
Bits 15–0 generate a compare event when the counter
matches this value.
Timer Compare Register 1
13 12 11 10
rw rw rw rw
1 1 1 1
Timer Compare Register 2
13 12 11 10
rw rw rw rw
1 1 1 1
Table 12-4. Timer Compare Register Description
Description
General-Purpose Timers
9 8 7 6 5
COMPARE
rw rw rw rw rw
1 1 1 1 1
0xFFFF
9 8 7 6 5
COMPARE
rw rw rw rw rw
1 1 1 1 1
0xFFFF
This field has a valid range 0x0000 to 0xFFFF.
Programming Model
0x(FF)FFF604
4 3 2 1 BIT 0
rw rw rw rw rw
1 1 1 1 1
0x(FF)FFF614
4 3 2 1 BIT 0
rw rw rw rw rw
1 1 1 1 1
Setting
12-9