Uart 2 Status/Control Register; Table 14-10 Uart 2 Status/Control Register Description - Motorola MC68VZ328 User Manual

Programming Model
14.4.8

UART 2 Status/Control Register

The UART 2 status/control register (USTCNT2) controls the overall operation of the UART 2 module.
The bit position assignments for this register are shown in the following register display. The settings for
this register are described in Table 14-10.
USTCNT2
BIT
14
15
RX
UEN
EN
TYPE rw rw
0 0
RESET
Table 14-10. UART 2 Status/Control Register Description
Name
UEN UART 2 Enable—This bit enables the UART 2 module. This bit
Bit 15 resets to 0.
Note: When the UART 2 module is first enabled after a hard
reset and before the interrupts are enabled, set the UEN and
RXEN bits and perform a word read operation on the URX
register to initialize the FIFO and character status bits.
RXEN Receiver Enable—This bit enables the receiver block. This bit
Bit 14 resets to 0.
TXEN Transmitter Enable—This bit enables the transmitter block.
Bit 13 This bit resets to 0.
CLKM Clock Mode Selection—This bit selects the receiver's operat-
Bit 12 ing mode. When this bit is low, the receiver is in 16x mode, in
which it synchronizes to the incoming datastream and samples
at the perceived center of each bit period. When this bit is high,
the receiver is in 1x mode, in which it samples the datastream
on each rising edge of the bit clock. In 1x mode, the bit clock is
driven by CLK16. This bit resets to 0.
PEN Parity Enable—This bit controls the parity generator in the
Bit 11 transmitter and the parity checker in the receiver.
ODD Odd Parity—This bit controls the sense of the parity generator
Bit 10 and checker. This bit has no function if the PEN bit is low.
STOP Stop Bit Transmission—This bit controls the number of stop
Bit 9 bits transmitted after a character. This bit has no effect on the
receiver, which expects one or more stop bits.
8/7 8- or 7-Bit—This bit controls the character length. When this
Bit 8 bit is set to 7-bit operation, the transmitter ignores data bit 7
and, when receiving, the receiver forces data bit 7 to 0.
14-20
UART 2 Status/Control Register
13 12 11 10 9
TX CL PE OD ST
EN KM N D OP
rw rw rw rw rw
0 0 0 0 0
Description
MC68VZ328 User's Manual
8 7 6 5
OD CT RX
8/7
EN SD FE
rw rw rw rw
0 0 0 0
0x0000
0 = UART 2 module is disabled
1 = UART 2 module is enabled
0 = Receiver is disabled and the
1 = Receiver is enabled
0 = Transmitter is disabled and the
1 = Transmitter is enabled
0 = 16x clock mode (asynchronous
1 = 1x clock mode (synchronous
0 = Parity is disabled
1 = Parity is enabled
0 = Even parity
1 = Odd parity
0 = One stop bit is transmitted
1 = Two stop bits are transmitted
0 = 7-bit transmit-and-receive
1 = 8-bit transmit-and-receive
0x(FF)FFF910
4 3 2 1
RX RX TX TX
HE RE EE HE
rw rw rw rw
0 0 0 0
Setting
receive FIFO is flushed
transmit FIFO is flushed
mode)
mode)
character length
character length
BIT
0
TX
AE
rw
0