Peripheral Clock Configuration - ST STM32L1 Series Application Note

Peripheral migration
Table 14. RCC registers used for peripheral access configuration (continued)
Register
Bus
L1 series
RCC_APB2RSTR
APB2 RCC_APB2ENR
RCC_APB2LPENR
1. The register configuring the peripherals is not present in STM32L1 Series, so it should not be needed from a migration-only
stand point
The configuration to access a given peripheral involves:
•
identifying the bus to which the peripheral is connected, refer to
•
selecting the right register according the needed action, refer to
For example, USART1 is connected to APB2 bus. In order to enable the USART1 clock, the
RCC_APB2ENR register needs to be configured as follows:
__HAL_RCC_USART1_CLK_ENABLE();
with STM32Cube HAL driver RCC API.
In order to disable USART1 clock during Sleep mode (to reduce power consumption) the
RCC_APB2SMENR register needs to be configured as follows:
__HAL_RCC_USART1_CLK_SLEEP_ENABLE();
with STM32Cube HAL driver RCC API.
4.5.3

Peripheral clock configuration

Some peripherals have a dedicated clock source independent from the system clock, that is
used to generate the clock required for their operation:
• USB:
In STM32L1 Series: the USB 48 MHz clock is derived from the PLL VCO clock which
should be at 96 MHz.
In STM32L4 Series: the USB 48 MHz clock is derived from one of the following
sources: main PLL VCO (PLLUSB1CLK), PLLSAI1 VCO (PLLUSB2CLK), MSI clock
(when the MSI clock is auto-trimmed with the LSE, it can be used by the USB OTG FS
device) or HSI48 internal oscillator (only on Cat. 4 devices).
•
SDIO/SDMMC:
In STM32L1 Series: the SDIO clock (SDIOCLK) is derived from the PLL VCO clock and
is equal to PLLVCO/2.
In STM32L4 Series: the SDMMC clock is derived from one of the three following
sources: main PLL VCO (PLLUSB1CLK), PLLSAI1 VCO (PLLUSB2CLK), MSI clock,
or HSI48 internal oscillator (only for Cat. 4 devices).
•
RTC and LCD:
The RTC and the LCD Glass clock share the same clock source (RTCCLK).
In STM32L1 Series: the RTC and LCD Glass clock is derived from one of the three
following sources: LSE, LSI, HSE divided by prescaler (/2, 4, 8, 16).
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Register
L4 series
RCC_APB2RSTR
RCC_APB2ENR
RCC_APB2SMENR
DocID027094 Rev 3
Comments
Used to [enter/exit] the APB2 peripheral from
reset
Used to [enable/disable] the APB2 peripheral
clock
Used to [enable/disable] the APB2 peripheral
clock in sleep mode
Table 9 on page 20
Table 14
AN4612
above.