Table 5. Cpu_Sm_2; Table 6. Cpu_Sm_3 - ST STM32L4 Series User Manual

SM CODE
Dependency on Device configuration
Initialization
Periodicity
Test for the diagnostic
Multiple-fault protection
Recommendations and known limitations
SM CODE
Description
Ownership
Detailed implementation
Error reporting
Fault detection time
Addressed fault model
Dependency on Device configuration
Initialization
Periodicity
Test for the diagnostic
Multiple-fault protection
Recommendations and known limitations
SM CODE
Description
Ownership
Detailed implementation
Error reporting
Fault detection time
Addressed fault model
UM2305 - Rev 10
None
Depends on implementation
Continuous
Not applicable
CPU_SM_0: Periodic core self-test software
None
Table 5. CPU_SM_2
Double computation in Application software
End user
A timing redundancy for safety-related computation is considered to detect transient faults
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affecting the Arm Cortex -M4 CPU subparts devoted to mathematical computations and data
access.
The guidelines for the implementation of the method are the following:
• The requirement needs be applied only to safety-relevant computation, which in case of
wrong result could interfere with the system safety functions. Such computation must be
therefore carefully identified in the original Application software source code
• Both mathematical operation and comparison are intended as computation.
• The redundant computation for mathematical computation is implemented by using
copies of the original data for second computation, and by using an equivalent formula if
possible
Depends on implementation
Depends on implementation
Transient
None
Depends on implementation
Continuous
Not applicable
CPU_SM_0: Periodic core self-test software
End user is responsible to carefully avoid that the intervention of optimization features of the
used compiler removes timing redundancies introduced according to this condition of use.
Table 6. CPU_SM_3
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Arm Cortex -M4 HardFault exceptions
ST
HardFault exception raise is an intrinsic safety mechanism implemented in Arm
core, mainly dedicated to intercept systematic faults due to software limitations or error in
software design (causing for example execution of undefined operations, unaligned address
access). This safety mechanism is also able to detect hardware random faults inside the CPU
bringing to such described abnormal operations.
High-priority interrupt event
Depends on implementation. Refer to functional documentation.
Permanent/transient
Hardware and software diagnostics
CPU_SM_1
CPU_SM_2
CPU_SM_3
UM2305
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Cortex -M4
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