System Bus Architecture/Busmatrix; Table 13. Mpu_Sm_1; Table 14. Bus_Sm_0 - ST STM32L4 Series User Manual

SM CODE
Detailed implementation
Error reporting
Fault detection time
Addressed fault model
Dependency on Device configuration
Initialization
Periodicity
Test for the diagnostic
Multiple-fault protection
Recommendations and known limitations
SM CODE
Description
Ownership
Detailed implementation
Error reporting
Fault detection time
Addressed fault model
Dependency on Device configuration
Initialization
Periodicity
Test for the diagnostic
Multiple-fault protection
Recommendations and known limitations
3.6.2

System bus architecture/BusMatrix

SM CODE
Description
Ownership
UM2305 - Rev 10
This method must be applied to MPU configuration registers (also unused by End
userApplication software).
Detailed information on the implementation of this method can be found in
Section 3.6.14 Extended interrupt and events controller
Refer to NVIC_SM_0
Refer to NVIC_SM_0
Refer to NVIC_SM_0
Refer to NVIC_SM_0
Refer to NVIC_SM_0
Refer to NVIC_SM_0
Refer to NVIC_SM_0
Refer to NVIC_SM_0
Refer to NVIC_SM_0
Table 13. MPU_SM_1
MPU software test
End user
This method tests MPU capability to detect and report memory accesses violating the policy
enforcement implemented by the MPU itself.
The implementation is based on intentionally performing read and write accesses outside the
memory areas allowed by the MPU region programming, and collecting and verifying related
generated error exceptions.
Test can be executed with the final MPU region programming or with a dedicated one.
Depends on implementation
Depends on implementation
Permanent
None
Depends on implementation
On demand
Not applicable
CPU_SM_0: Periodic core self-test software
Startup execution of this safety mechanism is recommended for multiple fault mitigations -
refer to Section 4.1.3 Notes on multiple-fault
Table 14. BUS_SM_0
Periodic software test for interconnections
End user
Hardware and software diagnostics
MPU_SM_0
(EXTI).
MPU_SM_1
scenario.
BUS_SM_0
UM2305
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