Table 120. Iic_Sm_2; Table 121. Iic_Sm_3 - ST STM32L4 Series User Manual

SM CODE
Detailed implementation
Error reporting
Fault detection time
Addressed fault model
Dependency on Device configuration
Initialization
Periodicity
Test for the diagnostic
Multiple-fault protection
Recommendations and known limitations
SM CODE
Description
Ownership
Detailed implementation
Error reporting
Fault detection time
Addressed fault model
Dependency on Device configuration
Initialization
Periodicity
Test for the diagnostic
Multiple-fault protection
Recommendations and known limitations
SM CODE
Description
Ownership
UM2305 - Rev 10
I2C communication module embeds protocol error checks (like overrun, underrun, packet
error etc.) conceived to detect network-related abnormal conditions. These mechanisms are
able anyway to detect a marginal percentage of hardware random failures affecting the
module itself.
Error flag raise and optional interrupt event generation
Depends on peripheral configuration (for example baud rate). Refer to functional
documentation.
Permanent/transient
None
Depends on implementation
Continuous
Not applicable
IIC_SM_2: Information redundancy techniques on messages
Adoption of SMBus option grants the activation of more efficient protocol-level hardware
checks such as CRC-8 packet protection.
Enabling related interrupt generation on the detection of errors is highly recommended.
Table 120. IIC_SM_2
Information redundancy techniques on messages
End user
This method is implemented adding to data packets transferred by I2C a redundancy check
(such as a CRC check, or similar one) with encoding capability. The checksum encoding
capability must be robust enough to guarantee at least 90% probability of detection for a
single bit flip in the data packet.
Consistency of data packet must be checked by Application software before consuming data.
Depends on implementation
Depends on implementation
Permanent/transient
None
Depends on implementation
On demand
Not applicable
CPU_SM_0: Periodic core self-test software
It is assumed that the remote I2C counterpart has an equivalent capability of performing the
check described.
To give an example on checksum encoding capability, using just a bit-by-bit addition is
unappropriated.
This method is superseded by IIC_SM_3 if hardware handled CRC insertion is possible.
Table 121. IIC_SM_3
CRC packet-level
ST
Hardware and software diagnostics
IIC_SM_1
IIC_SM_2
IIC_SM_3
UM2305
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