Table 35. Vsup_Sm_1; Table 36. Vsup_Sm_2 - ST STM32L4 Series User Manual

SM CODE
Detailed implementation
Error reporting
Fault detection time
Addressed fault model
Dependency on Device configuration
Initialization
Periodicity
Test for the diagnostic
Multiple-fault protection
Recommendations and known limitations
SM CODE
Description
Ownership
Detailed implementation
Error reporting
Fault detection time
Addressed fault model
Dependency on Device configuration
Initialization
Periodicity
Test for the diagnostic
Multiple-fault protection
Recommendations and known limitations
SM CODE
Description
Ownership
Detailed implementation
UM2305 - Rev 10
This method must be applied to configuration registers.
Detailed information on the implementation of this method can be found in
Section 3.6.14 Extended interrupt and events controller
Refer to NVIC_SM_0
Refer to NVIC_SM_0
Refer to NVIC_SM_0
Refer to NVIC_SM_0
Refer to NVIC_SM_0
Refer to NVIC_SM_0
Refer to NVIC_SM_0
Refer to NVIC_SM_0
Refer to NVIC_SM_0
Table 35. VSUP_SM_1
VSUP_SM_1
Supply voltage internal monitoring (PVD)
ST
The device features an embedded programmable voltage detector (PVD) that monitors the
V power supply and compares it to the V
DD
V drops below the V threshold or when V
DD PVD
Interrupt event generation
Depends on threshold programming. Refer to functional documentation.
Permanent/transient
None
Protection enable by the PVDE bit and the threshold setting in the Power control register
(PWR_CR)
Continuous
Direct test procedure for PVD efficiency is not available. PVD run-time hardware failures
leading to disabling such protection fall into multiple-fault scenario, from IEC61508
perspective. Related failures are adequately mitigated by the combination of safety
mechanisms reported in this table, field Multiple-fault protection.
DIAG_SM_0: Periodic read-back of hardware diagnostics configuration registers
Internal monitoring PVD has limited capability to address failures affecting STM32L4 and
STM32L4+ Series internal voltage regulator. Refer to
Internal monitoring PVD has limited capability to address failures affecting the internal voltage
regulator. Refer to Device FMEA for details.
Table 36. VSUP_SM_2
Independent watchdog
ST
Failures in the power supplies for digital logic (core or peripherals) may lead to alteration of
Application software timing, which can be detected by IWDG as safety mechanism introduced
to monitor Application software control flow. Refer to CPU_SM_1 and CPU_SM_6 for further
information.
Hardware and software diagnostics
VSUP_SM_0
(EXTI).
threshold. An interrupt can be generated when
PVD
is higher than the V
DD PVD
[1] for details.
VSUP_SM_2
UM2305
threshold.
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