Cyclic Redundancy-Check Calculation Unit (Crc); Table 63. Nvic_Sm_1; Table 64. Crc_Sm_0 - ST STM32L4 Series User Manual

SM CODE
Initialization
Periodicity
Test for the diagnostic
Multiple-fault protection
Recommendations and known limitations
SM CODE
Description
Ownership
Detailed implementation
Error reporting
Fault detection time
Addressed fault model
Dependency on Device configuration
Initialization
Periodicity
Test for the diagnostic
Multiple-fault protection
Recommendations and known limitations
3.6.15

Cyclic redundancy-check calculation unit (CRC)

SM CODE
Description
UM2305 - Rev 10
Values of configuration registers must be read after the boot before executing the first check.
Periodic
Not applicable
CPU_SM_0: Periodic core self-test software
This method addresses only failures affecting configuration registers, and not peripheral core
logic or external interface.
Attention must be paid to registers containing mixed combination of configuration and status
bits. Mask must be used before saving register contents affecting signature, and related
checks done, to avoid false positive detections.
Table 63. NVIC_SM_1
Expected and unexpected interrupt check
End user
According to IEC 61508:2 Table A.1 recommendations, a diagnostic measure for continuous,
absence or cross-over of interrupt must be implemented. The method of expected and
unexpected interrupt check is implemented at Application software level.
The guidelines for the implementation of the method are the following:
• The interrupts implemented on the MCU are well documented, also reporting, when
possible, the expected frequency of each request (for example, the interrupts related to
ADC conversion completion that come on a regular basis).
• Individual counters are maintained for each interrupt request served, in order to detect in
a given time frame the cases of a) no interrupt at all b) too many interrupt requests
("babbling idiot" interrupt source). The control of the time frame duration must be
regulated according to the individual interrupt expected frequency.
• Interrupt vectors related to unused interrupt source point to a default handler that
reports, in case of triggering, a faulty condition (unexpected interrupt).
• In case an interrupt service routine is shared between different sources, a plausibility
check on the caller identity is implemented.
• Interrupt requests related to non-safety-related peripherals are handled with the same
method here described, despite their originator safety classification.
Depends on implementation
Depends on implementation
Permanent/transient
None
Depends on implementation
Continuous
Not applicable
CPU_SM_0: Periodic core self-test software
In order to decrease the complexity of method implementation, it is suggested to use polling
technique (when possible) instead of interrupt for end system implementation.
Table 64. CRC_SM_0
CRC self-coverage
Hardware and software diagnostics
NVIC_SM_0
NVIC_SM_1
CRC_SM_0
UM2305
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