Table 67. Fsmc_Sm_2; Table 68. Fsmc_Sm_3 - ST STM32L4 Series User Manual

SM CODE
Detailed implementation
Error reporting
Fault detection time
Addressed fault model
Dependency on Device configuration
Initialization
Periodicity
Test for the diagnostic
Multiple-fault protection
Recommendations and known limitations
SM CODE
Description
Ownership
Detailed implementation
Error reporting
Fault detection time
Addressed fault model
Dependency on Device configuration
Initialization
Periodicity
Test for the diagnostic
Multiple-fault protection
Recommendations and known limitations
SM CODE
Description
Ownership
Detailed implementation
UM2305 - Rev 10
If FSMC interface is used to connect an external memory where safety-relevant data are
stored, information redundancy techniques for stored data are able to address faults affecting
the FSMC interface. The possible techniques are:
• using redundant copies of safety-relevant data and performing coherence check before
consuming
• organizing data in arrays and computing the checksum field to check before use
Depends on implementation
Depends on implementation
Permanent/transient
FSMC interface is available only on selected part numbers.
Depends on implementation
On demand
Not applicable
CPU_SM_0: Periodic core self-test software
This mechanism must be used just if FSMC external memory is used to store safety-related
data.
This safety mechanism can overlap with information redundancy techniques implemented at
system level to address failure of physical device connected to FSMC port.
Table 67. FSMC_SM_2
FSMC_SM_2
Periodic read-back of FSMC configuration registers
End user
This method must be applied to FSMC configuration registers.
Detailed information on the implementation of this method can be found in
Section 3.6.14 Extended interrupt and events controller
Refer to NVIC_SM_0
Refer to NVIC_SM_0
Refer to NVIC_SM_0
FSMC interface is available only on selected part numbers.
Refer to NVIC_SM_0
Refer to NVIC_SM_0
Refer to NVIC_SM_0
Refer to NVIC_SM_0
Refer to NVIC_SM_0
Table 68. FSMC_SM_3
ECC engine on NAND interface in FSMC module
ST
The FMC NAND Card controller includes two error correction code computation hardware
blocks, one per memory bank. They reduce the host CPU workload when processing the ECC
by software.
ECC mechanism protects data integrity on the external memory connected to NAND port.
Hardware and software diagnostics
FSMC_SM_1
(EXTI).
FSMC_SM_3
UM2305
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