SM CODE
Dependency on Device configuration
Initialization
Periodicity
Test for the diagnostic
Multiple-fault protection
Recommendations and known limitations
SM CODE
Description
Ownership
Detailed implementation
Error reporting
Fault detection time
Addressed fault model
Dependency on Device configuration
Initialization
Periodicity
Test for the diagnostic
Multiple-fault protection
Recommendations and known limitations
SM CODE
Description
Ownership
Detailed implementation
Error reporting
Fault detection time
Addressed fault model
Dependency on Device configuration
Initialization
Periodicity
Test for the diagnostic
Multiple-fault protection
UM2305 - Rev 10
Refer to NVIC_SM_0
Refer to NVIC_SM_0
Refer to NVIC_SM_0
Refer to NVIC_SM_0
Refer to NVIC_SM_0
Refer to NVIC_SM_0
Table 41.
CLK_SM_1
Clock security system (CSS)
ST
The clock security system (CSS) detects the loss of high-speed external (HSE) oscillator clock
activity and executes the corresponding recovery action, such as:
•
switch-off HSE
•
commutation on the HIS
•
generation of related NMI
NMI
Depends on implementation (clock frequency value)
Permanent/transient
None
CSS protection must be enabled through Clock interrupt register (RCC_CIR) after boot.
Continuous
CLK_SM_0: Periodic read-back of configuration registers
CPU_SM_5: External watchdog
It is recommended to carefully read reference manual instruction on NMI generation, in order
to correctly managing the faulty situation by Application software.
Table 42.
CLK_SM_2
Independent watchdog
ST
The independent watchdog IWDG is able to detect failures in internal main MCU clock (lower
frequency).
Reset signal generation
Depends on implementation (watchdog timeout interval)
Permanent
None
IWDG activation. It is recommended to use the hardware watchdog in Option byte settings
(IWDG is automatically enabled after reset).
Continuous
Refer to CPU_SM_6.
CPU_SM_1: Control flow monitoring in Application software
Hardware and software diagnostics
CLK_SM_0
CLK_SM_1
CLK_SM_2
UM2305
page 30/110
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