ST STM32L476G-EVAL Manuals

Manuals and User Guides for ST STM32L476G-EVAL. We have 1 ST STM32L476G-EVAL manual available for free PDF download: User Manual

ST STM32L476G-EVAL User Manual (100 pages)

Brand: ST | Category: Motherboard | Size: 3 MB

Figure 1. STM32L476G-EVAL Evaluation Board
1
Table of Contents
2
Overview
9
Features
9
Demonstration Software
10
Order Code
10
Unpacking Recommendations
10
Hardware Layout and Configuration
11
Figure 2. STM32L476G-EVAL Hardware Block Diagram
11
Figure 3. STM32L476G-EVAL Main Component Layout
12
St-Link/V2-1
13
Drivers
13
Figure 4. USB Composite Device
13
ST-LINK/V2-1 Firmware Upgrade
14
ETM Trace
14
Table 1. Setting of Configuration Elements for Trace Connector CN12
14
Power Supply
15
Supplying the Board through ST-LINK/V2-1 USB Port
15
Using ST-LINK/2-1 Along with Powering through CN22 Power Jack
16
Figure 5. CN22 Power Jack Polarity
16
Table 2. Power-Supply-Related Jumper Settings
17
Clock References
19
Reset Sources
19
Table 3. X1-Crystal-Related Solder Bridge Settings
19
Table 4. X2-Crystal-Related Solder Bridge Settings
19
Boot
20
Boot Options
20
Table 5. Boot Selection Switch
20
Table 6. Bootloader-Related Jumper Setting
20
Bootloader Limitations
21
Audio
21
Digital Microphones
22
Headphones Outputs
22
Table 7. Digital Microphone-Related Jumper Settings
22
Limitations in Using Audio Features
23
USB OTG FS Port
23
STM32L476G-EVAL Used as USB Device
23
Figure 6. CN20, CN21 Top View
23
STM32L476G-EVAL Used as USB Host
24
Configuration Elements Related with USB OTG FS Port
24
Table 8. Configuration Elements Related with USB OTG FS Port
24
Limitations in Using USB OTG FS Port
25
Operating Voltage
25
RS-232 and Irda Ports
25
RS-232 Port
25
Irda Port
26
Limitations
26
Operating Voltage
26
LPUART Port
26
Table 9. Settings of Configuration Elements for RS-232 and Irda Ports
26
Microsd Card
27
Limitations
27
Operating Voltage
27
Table 10. Hardware Settings for LPUART
27
Table 11. Terminals of CN18 Microsd Slot
27
Motor Control
28
Table 12. Motor Control Terminal and Function Assignment
28
Board Modifications to Enable Motor Control
29
Figure 7. PCB Top-Side Rework for Motor Control
30
Limitations
31
Can
31
Figure 8. PCB Underside Rework for Motor Control
31
Limitations
32
Operating Voltage
32
Extension Connectors CN6 and CN7
32
LCD Glass Module Daughterboard
32
Table 13. CAN Related Jumpers
32
Figure 9. LCD Glass Module Daughterboard in Display Position
33
Table 14. LCD-Daughterboard-Related Configuration Elements
34
Figure 10. LCD Glass Module Daughterboard in I/O-Bridge Position
34
Table 15. LCD Glass Element Mapping - Segments 0 to 9
36
Table 16. LCD Glass Element Mapping - Segments 10 to 19
36
Table 17. LCD Glass Element Mapping - Segments 20 to 29
36
Limitations
37
Table 18. LCD Glass Element Mapping - Segments 30 to 39
37
Figure 11. LCD Glass Display Element Mapping
38
TFT LCD Panel
39
Table 19. Access to TFT LCD Resources with FMC Address Lines A0 and A1
39
Table 20. Assignment of CN19 Connector Terminals of TFT LCD Panel
39
User Leds
40
Physical Input Devices
40
Table 21. Port Assignment for Control of LED Indicators
40
Table 22. Port Assignment for Control of Physical Input Devices
40
Limitations
41
Operational Amplifier and Comparator
41
Operational Amplifier
41
Table 23. Setting of Jumpers Related with Potentiometer and LDR
41
Comparator
42
Analog Input, Output, VREF
42
SRAM Device
42
Limitations
43
Operating Voltage
43
NOR Flash Memory Device
43
Table 24. SRAM Chip Select Configuration
43
Limitations
44
Operating Voltage
44
Eeprom
44
Rf-Eeprom
44
Table 25. nor Flash Memory-Related Configuration Elements
44
Quad-SPI Flash Memory Device
45
Table 26. Configuration Elements Related with Quad-SPI Device
45
Limitations
46
Operating Voltage
46
Touch-Sensing Button
46
Table 27. Touch-Sensing-Related Configuration Elements
47
Limitations
48
Smartcard, SWP
48
Table 28. Assignment of Ports for ST8024CDR Control
48
Table 29. Configuration Elements Related with Smartcard and SWP
49
Limitations
50
Operating Voltage
50
Near-Field Communication (NFC)
50
Figure 12. NFC Board Plugged into STM32L476G-EVAL Board
50
Dual-Channel Sigma-Delta Modulators STPMS2L
51
STPMS2L Presentation
51
Table 30. CN13 NFC Connector Terminal Assignment
51
STPMS2L Settings
52
STPMS2L Power Metering
52
Figure 13. Routing of STPMS2L Dual-Channel Sigma-Delta Modulators
52
Figure 14. Power Measurement Principle Schematic Diagram
53
Figure 15. STPMS2L Power Metering Schematic Diagram
53
STPMS2L for PT100 Measurement
54
Limitations
54
STM32L476ZGT6 Current Consumption Measurement
54
Figure 16. Temperature Measurement Principle Schematic Diagram
54
IDD Measurement Principle - Analog Part
55
Low-Power-Mode IDD Measurement Principle - Logic Part
56
Figure 17. Schematic Diagram of the Analog Part of IDD Measurement
56
Figure 18. Schematic Diagram of Logic Part of Low-Power-Mode IDD Measurement
57
IDD Measurement in Dynamic Run Mode
58
Calibration Procedure
58
Figure 19. Low Power Mode IDD Measurement Timing
58
Table 31. JP11 Jumper Settings During IDD Measurement with Calibration
59
Connectors
60
D-Sub Male Connector CN9
60
Power Connector CN22
60
Table 32. RS-232 D-Sub (DE-9M) Connector CN9 with HW Flow Control and ISP Support
60
Figure 20. RS-232 D-Sub (DE-9M) 9-Pole Connector (Front View)
60
Figure 21. Power Supply Connector CN22 (Front View)
60
LCD Daughterboard Connectors CN11 and CN14
61
Table 33. CN11 and CN14 Daughterboard Connectors
61
Extension Connectors CN6 and CN7
62
Table 34. Daughterboard Extension Connector CN6
62
Table 35. Daughterboard Extension Connector CN7
63
ST-LINK/V2-1 Programming Connector CN16
65
ST-LINK/V2-1 Standard-B USB Connector CN17
65
Figure 22. USB Type B Connector CN17 (Front View)
65
JTAG Connector CN15
66
Table 36. USB Standard-B Connector CN17
66
Table 37. JATG Debugging Connector CN15
66
Figure 23. JTAG Debugging Connector CN15 (Top View)
66
ETM Trace Debugging Connector CN12
67
Table 38. Trace Debugging Connector CN12
67
Figure 24. Trace Debugging Connector CN12 (Top View)
67
Microsd Card Connector CN18
68
ADC/DAC Connector CN8
68
Table 39. Microsd Card Connector CN18
68
Figure 25. Microsd Card Connector CN18
68
Figure 26. Analog Input-Output Connector CN8 (Top View)
68
RF-EEPROM Daughterboard Connector CN3
69
Motor Control Connector CN2
69
Table 40. Analog Input-Output Connector CN8
69
Table 41. RF-EEPROM Daughterboard Connector CN3
69
Figure 27. RF EEPROM Daughterboard Connector CN3 (Front View)
69
Figure 28. Motor Control Connector CN2 (Top View)
69
USB OTG FS Micro-AB Connector CN1
70
Table 42. Motor Control Connector CN2
70
Table 43. USB OTG FS Micro-AB Connector CN1
70
Figure 29. USB OTG FS Micro-AB Connector CN1 (Front View)
70
CAN D-Sub Male Connector CN5
71
NFC Connector CN13
71
Table 44. CAN D-Sub (DE-9M) 9-Pins Male Connector CN5
71
Table 45. NFC CN13 Terminal Assignment
71
Figure 30. CAN D-Sub (DE-9M) 9-Pole Male Connector CN5 (Front View)
71
Figure 31. NFC Female Connector CN13 (Top View)
71
Appendix A Schematic Diagrams
73
Figure 32. STM32L476G-EVAL Top Schematic Diagram
73
Figure 33. MCU, LCD Daughterboard and I/O Expander Interfaces - Schematic Diagram
74
Figure 34. STM32L476G-EVAL MCU Part 1 - Schematic Diagram
75
Figure 35. STM32L476G-EVAL MCU Part 2 - Schematic Diagram
76
Figure 36. LCD Glass Module Daughterboard Connectors - Schematic Diagram
77
Figure 37. I/O Expander Schematic Diagram
78
Figure 38. Power Supply Schematic Diagram
79
Figure 39. Smartcard, SWP and NFC - Schematic Diagram
80
Figure 40. USART and Irda - Schematic Diagram
81
Figure 41. SRAM and nor Flash Memory Devices - Schematic Diagram
82
Figure 42. TFT LCD Schematic Diagram
83
Figure 43. Extension Connector Schematic Diagram
84
Figure 44. Quad-SPI Flash Memory Device Schematic Diagram
85
Figure 45. Microsd Card Schematic Diagram
86
Figure 46. Physical Control Peripherals - Schematic Diagram
87
Figure 47. CAN Transceiver Schematic Diagram
88
Figure 48. Touch-Sensing Device Schematic Diagram
89
Figure 49. USB_OTG_FS Port Schematic Diagram
90
Figure 50. IDD Measurement Schematic Diagram
91
Figure 51. Audio Codec Device Schematic Diagram
92
Figure 52. STPMS2L and PT100 Schematic Diagram
93
Figure 53. RF-EEPROM and EEPROM Schematic Diagram
94
Figure 54. Motor Control Connector Schematic Diagram
95
Figure 55. JTAG and Trace Debug Connectors - Schematic Diagram
96
Figure 56. ST-LINK/V2-1 Schematic Diagram
97
Table 46. Document Revision History
99

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