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Texas Instruments TLK3134 Data Manual

4-channel multi-rate transceiver
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TLK3134
4-Channel Multi-Rate Transceiver
Data Manual
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Literature Number: SLLS838F
May 2007 – Revised December 2009

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  • Page 1 TLK3134 4-Channel Multi-Rate Transceiver Data Manual PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Literature Number: SLLS838F...

  • Page 2: Table Of Contents

    Inter-Packet Gap Management ..............2.7.26 Clock Tolerance Compensation (CTC) ....................2.7.27 Parallel to Serial ....................2.7.28 Serial to Parallel ..................2.7.29 High Speed CML Output ..................2.7.30 High Speed Receiver ......................2.7.31 Loopback Contents Copyright © 2007–2009, Texas Instruments Incorporated...
  • Page 3 Package Dissipation Rating ..............APPENDIX A – Frequency Ranges Supported ................. Recovered Byte Clock Jitter Cleaner Mode: ............APPENDIX B – Jitter Cleaner PLL External Loop Filter ..................APPENDIX C – Device Test Mode Contents Copyright © 2007–2009, Texas Instruments Incorporated...
  • Page 4 List of Figures ....................System Block Diagram – XAUI ..................System Block Diagram – XAUI Backplane ................Block Diagram – TLK3134 Clocking Architecture ..................... Quad 10-Bit SERDES Application ................XAUI Mode – XAUI (Serial) Loopback Application ............... XAUI Mode - XGMII (Parallel ) Loopback Application ................
  • Page 5 ......................4-14 HSTL I/O Schematic ........................4-15 JTAG Timing ............4-16 TLK3134 Application Mode vs Interface Timing Mode Support ..............4-17 PACKAGE Information (Package Designator = ZEL) ..................4-18 Worst Case Device Power Dissipation ............... Reference Clock Selection – XAUI – 10 GbE Mode ............
  • Page 6 LANE_0_TEST_ERROR_COUNT .................... 2-38 LANE_1_ TEST_ERROR_COUNT .................... 2-39 LANE_2_ TEST_ERROR_COUNT .................... 2-40 LANE_3_ TEST_ERROR_COUNT ............. 2-41 10GFCCJPAT_CRPAT_CJPAT_TEST_ERROR_COUNT_1 ............. 2-42 10GFCCJPAT_CRPAT_CJPAT_TEST_ERROR_COUNT_2 ..................... 2-43 LANE_0_EOP_ERROR_COUNT ..................... 2-44 LANE_1_EOP_ERROR_COUNT ..................... 2-45 LANE_2_EOP_ERROR_COUNT ..................... 2-46 LANE_3_EOP_ERROR_COUNT List of Tables Copyright © 2007–2009, Texas Instruments Incorporated...
  • Page 7 2-85 PHY_TEST_PATTERN_COUNTER ..................2-86 PHY_CRPAT_PATTERN_COUNTER_1 ..................2-87 PHY_CRPAT_PATTERN_COUNTER_2 ....................2-88 PHY_TEST_MODE_CONTROL ...................... 2-89 PHY_CHANNEL_STATUS ................2-90 PHY_PRBS_HIGH_SPEED_TEST_COUNTER ................... 2-91 PHY_EXT_ADDRESS_CONTROL ....................2-92 PHY_EXT_ADDRESS_DATA ......................2-93 SERDES_PLL_CONFIG ......................2-94 PLL Multiplier Control List of Tables Copyright © 2007–2009, Texas Instruments Incorporated...
  • Page 8 DIE_ID_6 .......................... 2-133 DIE_ID_5 .......................... 2-134 DIE_ID_4 .......................... 2-135 DIE_ID_3 .......................... 2-136 DIE_ID_2 .......................... 2-137 DIE_ID_1 .......................... 2-138 DIE_ID_0 ......................... 2-139 EFUSE_STATUS ......................2-140 EFUSE_CONTROL ................... 2-141 HSTL_INPUT_TERMINATION_CONTROL ................... 2-142 HSTL_OUTPUT_SLEWRATE_CONTROL List of Tables Copyright © 2007–2009, Texas Instruments Incorporated...
  • Page 9 Voltage Supply and Reference Pins ....................Jitter Cleaner Related Pins ................... XAUI Driver Template Parameters ............Parallel Interface – Valid Signal Operational Mode Definitions ....................Device Mode Configuration ..................Device Test Mode Pin Configuration List of Tables Copyright © 2007–2009, Texas Instruments Incorporated...
  • Page 10 TLK3134 SLLS838F – MAY 2007 – REVISED DECEMBER 2009 www.ti.com List of Tables Copyright © 2007–2009, Texas Instruments Incorporated...

  • Page 11: Introduction

    Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Copyright © 2007–2009, Texas Instruments Incorporated Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not...

  • Page 12: Pin Out

    Many common applications may be enabled by way of externally available control pins. Detailed control of the TLK3134 on a per channel basis is available by way of accessing a register space of control bits available through a two-wire access port called the Management Data Input/Output (MDIO) interface.

  • Page 13: System Block Diagram - Xaui

    TLK3134 TLK3134 Packet Processor RC(3:0) RCLK RD(31:0) Figure 1-1. System Block Diagram – XAUI Figure 1-2 shows an example system block diagram for TLK3134 used to provide the system backplane interconnect. Line Card RCLK RDP/N[3:0] RD(31:0) RC(3:0) MAC/ FRAMER/ PHY/...

  • Page 14: Detailed Description

    The TLK3134 jitter cleaner may only be used on the recovered byte clock from Channel 0. If the jitter cleaner is used to clean the recovered byte clock, it may...

  • Page 15: Operating Frequency Range

    SLLS838F – MAY 2007 – REVISED DECEMBER 2009 Operating Frequency Range The TLK3134 is optimized for operation at a serial data rate of 600 Mbit/s through 3.75 Gbit/s. The external differential (optionally single-ended) reference clock has a large operating frequency range allowing support for many different applications.

  • Page 16: Quad 10-Bit Serdes Application

    TLK3134 Figure 2-1. Quad 10-Bit SERDES Application Figure 2-2 shows the TLK3134 in a XAUI Loopback Application. It is possible to configure XAUI side loopback in SERDES mode for all 4 channels on an individual basis. TLK3134 XGXS CORE Figure 2-2.

  • Page 17: Custom Independent Configuration Application

    It also supports a comprehensive series of built-in tests for self-test purposes including PRBS generation and verification, CRPAT, CJPAT, Mixed/High/Low Frequency testing. The TLK3134 operates with a 1.2 V core voltage supply, a 1.5/1.8 V HSTL I/O voltage supply and a 2.5 V LVCMOS/bias supply.

  • Page 18: Tlk3134 Block Diagram

    RXD(31:0) TBI/ RTBI RXC(7:0) Jitter JTAG Cleaner TRSTN PRTAD[4:0] MDIO MDIO Figure 2-5. TLK3134 Block Diagram Following is a more detailed block diagram description of the XAUI core. Test CHANNEL 3 mode Test CHANNEL 2 mode Test CHANNEL 1 mode...

  • Page 19: Detailed Xaui/1000Base-X Core Block Diagram

    Baud Synthesizer Clock Interpolator and Clock Recovery Recovered Clock RCLK Serial to Parallel Parallel Data Out Comma Detect Figure 2-7. Block Diagram of SERDES Core Detailed Description Copyright © 2007–2009, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TLK3134...

  • Page 20: Device Operation Modes

    (2) Default Mode if ST Primary Chip Input Pin “0”, CODE Primary Chip Input Pin “0”. (3) All Clause 22 Registers are Per Device Channel. Detailed Description Copyright © 2007–2009, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TLK3134...

  • Page 21: Parallel Interface Modes - Detailed Description

    SLLS838F – MAY 2007 – REVISED DECEMBER 2009 Parallel Interface Modes - Detailed Description The TLK3134 has several parallel interface modes. The major parallel interface modes of operation are presented below: 2.7.1 XAUI/10GFC Mode Table 2-3. XAUI – Lane To Functional Pin Mapping (XAUI_ORDER = 1)

  • Page 22: Rgmii Mode (Reduced Gigabit Media Independent Interface)

    {RX_DV,DataN[3:0]} and {RX_DV^RX_ER, {RX_DV^RX_ER, RXD_[4:0] {RX_DV,Data0[3:0]} {RX_DV,Data1[3:0]} {RX_DV^RX_ER,DataN[7:4]} swap Data0[7:4]} Data1[7:4]} locations. Figure 2-8. RGMII – Individual Channel Byte Ordering – Channel 0 Example Detailed Description Copyright © 2007–2009, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TLK3134...

  • Page 23: Rtbi Mode (Reduced Ten Bit Interface)

    TXD_[4:0] Data0[4:0] Data0[9:5] Data0[9:5] Data0[4:0] RXCLK_[0] RXCLK_[0] RXD_[4:0] RXD_[4:0] Data0[4:0] Data0[9:5] Data0[9:5] Data0[4:0] Figure 2-9. RTBI – Individual Channel Byte Ordering – Channel 0 Example Detailed Description Copyright © 2007–2009, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TLK3134...

  • Page 24: Tbi Mode (Ten Bit Interface)

    SDR Falling Edge Aligned Timing TXCLK_[0] TXC_[4],TXC_[0],TXD_[7:0] Data0[9:0] Data1[9:0] RXCLK_[0] RXC_[4],RXC_[0],RXD_[7:0] Data0[9:0] Data1[9:0] Figure 2-10. TBI – Individual Channel Byte Ordering – Channel 0 Example Detailed Description Copyright © 2007–2009, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TLK3134...

  • Page 25: Gmii Mode (Gigabit Media Independent Interface)

    SDR Falling Edge Aligned Timing TXCLK_[0] TXC_[0],TXC_[4],TXD_[7:0] {TX_EN,TX_ER,Data0[7:0]} {TX_EN,TX_ER,Data1[7:0]} RXCLK_[0] RXC_[0],RXC_[4],RXD_[7:0] {RX_DV,RX_ER,Data0[7:0]} {RX_DV,RX_ER,Data1[7:0]} Figure 2-11. GMII – Individual Channel Byte Ordering – Channel 0 Example Detailed Description Copyright © 2007–2009, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TLK3134...

  • Page 26: Ebi Mode (Eight Bit Interface)

    SDR Falling Edge Aligned Timing TXCLK_[0] TXD_[7:0] Data0[7:0] Data1[7:0] RXCLK_[0] RXD_[7:0] Data0[7:0] Data1[7:0] Figure 2-12. EBI – Individual Channel Byte Ordering – Channel 0 Example Detailed Description Copyright © 2007–2009, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TLK3134...

  • Page 27: Rebi Mode (Reduced Eight Bit Interface)

    Data0[3:0] Data0[7:4] Data0[7:4] Data0[3:0] TXD_[3:0] RXCLK_[0] RXCLK_[0] RXD_[3:0] Data0[3:0] Data0[7:4] RXD_[3:0] Data0[7:4] Data0[3:0] Figure 2-13. REBI – Individual Channel Byte Ordering – Channel 0 Example Detailed Description Copyright © 2007–2009, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TLK3134...

  • Page 28: Nbi Mode (Nine Bit Interface Mode)

    RXC_[0],RXD_[7:0] Data0[8:0] = {Control Bit, Data Byte} Data1[8:0] = {Control Bit, Data Byte} Figure 2-14. NBI – Individual Channel Byte Ordering – Channel 0 Example Detailed Description Copyright © 2007–2009, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TLK3134...

  • Page 29: Rnbi Mode (Reduced Nine Bit Interface)

    Data0[4:0] = {Control Bit, Data {Control Bit, Data {Data Byte[4:0]} {Data Byte[4:0]} Byte[7:5]} Byte[7:5]} Figure 2-15. RNBI – Individual Channel Byte Ordering – Channel 0 Example Detailed Description Copyright © 2007–2009, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TLK3134...

  • Page 30: Tbid Mode (Ten Bit Interface Ddr)

    DDR Source Aligned Timing TXCLK_[0] TXC_[4], TXC_[0], Data0[9:0] Data1[9:0] TXD_[7:0] RXCLK_[0] RXC_[4], RXC_[0], Data0[9:0] Data1[9:0] RXD_[7:0] Figure 2-16. TBID – Individual Channel Byte Ordering – Channel 0 Example Detailed Description Copyright © 2007–2009, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TLK3134...

  • Page 31: Nbid Mode (Nine Bit Interface Ddr)

    Data0[8:0] = {Control Data1[8:0] = {Control RXC_[0], RXD_[7:0] Bit, Data Byte} Bit, Data Byte} Figure 2-17. NBID – Individual Channel Byte Ordering – Channel 0 Example Detailed Description Copyright © 2007–2009, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TLK3134...

  • Page 32: 2.7.12 Parallel Interface Clocking Modes

    2.7.12 Parallel Interface Clocking Modes The TLK3134 supports source centered timing and source aligned DDR timing on the parallel receive output bus. TLK3134 also supports rising edge aligned and falling edge aligned SDR timing on the parallel receive output bus. See Figure 2-18 for more details.

  • Page 33: 2.7.13 Parallel Interface Data

    2.7.14 Transmission Latency For each channel, the data transmission latency of the TLK3134 is defined as the delay from the rising or falling edge of the selected transmit clock when valid data is on the transmit data pins to the serial...

  • Page 34: 2.7.15 Channel Clock To Serial Transmit Clock Synchronization

    FibreChannel standards. This provides good transition density for clock recovery and improves error checking. The TLK3134 will internally encode and decode the data such that the user reads and writes actual 8-bit data on each channel. The encoder and decoder functions can optionally be enabled or disabled on a per channel basis.

  • Page 35: Valid K-Codes

    Similarly, reception of K-characters is reported by the receive control pins, RXC(3:0). When receive control pin is asserted, the corresponding byte on the receive data bus should be interpreted as a K-character. The TLK3134 will transmit and receive all of the twelve valid K-characters as defined in Table 2-15.

  • Page 36: 2.7.18 Comma Detect And 8B/10B Decoding

    Code word error or running disparity error 2.7.19 Channel Initialization and Synchronization The TLK3134 has a synchronization state machine which is responsible for handling link initialization and synchronization for each channel. The initialization and synchronization state diagram is provided in Figure 2-22.

  • Page 37: 2.7.20 Channel State Descriptions

    While in this state the TLK3134 will set the Lane Sync bit to '0' for the particular channel in MDIO register bits 4/5.24.3:0 indicating the lane is not synchronized.

  • Page 38: 2.7.21 End Of Packet Error Detection

    2.7.22 Fault Detection and Reporting The TLK3134 will detect and report local faults as well as forward both local and remote faults as defined in the IEEE 802.3ae 10Gbps Ethernet Standard to aid in fault diagnosis. All faults detected by the TLK3134 are reported as local faults to the upper layer protocols.

  • Page 39: 2.7.23 Receive Synchronization And Skew Compensation

    Note that the TLK3134 will not generate a remote fault indication nor any other type of Q. 2.7.23 Receive Synchronization and Skew Compensation In XAUI mode, the TLK3134 has a FIFO enabled on the receive data path coming from each serial link to compensate for channel skew and clock phase and frequency tolerance differences between the recovered clocks for each channel and the receive output clock RCLK.

  • Page 40: 2.7.24 Column State Descriptions

    Inter-Packet Gap, the column state machine will transition to state FAIL1. (2) The XGXS Lane Alignment bit = '0' will cause a local fault to be output on the receive data bus. Detailed Description Copyright © 2007–2009, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s):...

  • Page 41: 2.7.25 Inter-Packet Gap Management

    Standard, a valid packet must begin on TXD(7:0) of the XGMII. However, due to variable packet sizes, the IPG can begin on any channel. The TLK3134 will replace idle codes latched on the same XGMII clock edge as the end of packet code with /K/ codes (as shown in Figure 2-26).

  • Page 42: Inter-Packet Gap Management

    XAUI channel and allow output of the aligned 32 bit wide data on a single edge of the receive clock, RCLK, as shown in Figure 2-25. Detailed Description Copyright © 2007–2009, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TLK3134...

  • Page 43: Ipg Management State Machine

    16 ≤ Acnt ≤ 31. Acnt is decremented each time a column of A characters is generated. nextKR A randomly-generated Boolean that can assume the value K or R. ||T|| Terminate Character Column (Terminate Character in Any Lane). Detailed Description Copyright © 2007–2009, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TLK3134...

  • Page 44: Clock Tolerance Compensation (Ctc)

    FIFOs on the receive/transmit data path. The TLK3134 provides compensation for these differences in clock frequencies via the insertion or the removal of /R/ characters on all channels, as shown in...

  • Page 45: 2.7.27 Parallel To Serial

    The high speed data output driver is implemented using Current Mode Logic (CML) with integrated pull up resistors requires no external components. The line can be directly coupled or AC coupled. Under many circumstances, AC coupling is desirable. Detailed Description Copyright © 2007–2009, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TLK3134...

  • Page 46: Example High Speed I/O Ac Coupled Mode

    Current Mode Logic (CML) drivers often require external components. The disadvantage of the external component is a limited edge rate due to package and line parasitic. The CML driver on TLK3134 has on-chip 50Ω termination resistors terminated to VDDT, providing optimum performance for increased speed requirements.

  • Page 47: 2.7.30 High Speed Receiver

    PHY address field on the MDIO protocol (PA[4:0]) matches {PRTAD[4:1], 1’b0}. PRTAD[0] pin acts as device id pin where it determines whether TLK3134 is a DTE or PHY device. The device ID is required to be either 4 (PHY) or 5 (DTE), so only one bit is required to differentiate. If PRTAD[0] is a 0, then a PHY device is selected for the XGXS.

  • Page 48: 2.7.34 Mdio Protocol Timing

    4 individual channels in TLK3134 are classified as 4 different ports. So for any PRTAD[4:2] value there will be 4 ports per TLK3134. TLK3134 will respond if the 3 MSB’s of PHY address field on MDIO protocol (PA[4:2]) matches PRTAD[4:2]. 2 LSB’s of PHY address field (PA[1:0]) will determine which channel/port within TLK3134 to respond.

  • Page 49: 2.7.35 Clause 22 Indirect Addressing

    Data Idle Preamble Code Addr Addr Note that the 1 in the Turn Around section is externally pulled up, and driven to Z by TLK3134 Figure 2-36. CL22 – Management Interface Read Timing MDIO PA [4:0] RA 4 RA 0 32 "1's"...

  • Page 50: Cl22 - Indirect Address Method - Address Write

    Figure 2-41. CL22 – Indirect Address Method – Data Read The IEEE 802.3 Clause 22/45 specification defines many of the registers, and additional registers have been implemented for expanded functionality. Detailed Description Copyright © 2007–2009, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TLK3134...

  • Page 51: Programmers Reference

    OUI c:r Organizationally unique identifier. Table 2-22. XS_DEVICE_IDENTIFIER_2 ADDRESS: 0x0003 DEFAULT: 0x50D0 BIT(s) NAME DESCRIPTION ACCESS 4/5.3.15:0 OUI c:r Device identifier. Manufacturer model and revision number Detailed Description Copyright © 2007–2009, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TLK3134...

  • Page 52: Xs_Speed_Ability

    0 = No fault condition on receive path Table 2-27. XS_PACKAGE_IDENTIFIER_1 ADDRESS: 0x000E DEFAULT: 0x4000 BIT(s) NAME DESCRIPTION ACCESS 4/5.14.15:0 OUI c:r Organizationally unique identifier. Detailed Description Copyright © 2007–2009, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TLK3134...

  • Page 53: Xs_Package_Identifier_2

    When set, enables the verification of CRPAT test mode. (Default 1’b0) 4/5.32769.0 CJPAT Check Enable When set, enables the verification of CJPAT test mode. (Default 1’b0) Detailed Description Copyright © 2007–2009, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TLK3134...

  • Page 54: Tx_Fifo_Status

    This counter reflects errors for High, Medium or Low Frequency test Lane 0 test pattern 4/5.32774.15:0 patterns for lane 0. This counter increments by one for each received RO/COR error counter character that has error. Detailed Description Copyright © 2007–2009, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TLK3134...

  • Page 55: Lane_1_ Test_Error_Count

    Counter will hold on to its value when align_status goes low or when the counter reaches its maximum value. It will be cleared when it is read. Detailed Description Copyright © 2007–2009, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s):...

  • Page 56: Lane_0_Code_Error_Count

    Counter will hold on to its value when align_status goes low or when the counter reaches its maximum value. It will be cleared when it is read. Detailed Description Copyright © 2007–2009, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s):...

  • Page 57: Lane_2_Code_Error_Count

    When high, reverses the order of bits in the parallel data received from the 4/5.32791. 1 XGMII TX bit order XGMII interface each lane. (Default 1’b0) Detailed Description Copyright © 2007–2009, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TLK3134...

  • Page 58: Loopback_Control

    Table 2-58. RX_CTC_INSERT_COUNT ADDRESS: 0x801B DEFAULT: 0xFFFD BIT(s) NAME DESCRIPTION ACCESS 4/5.32795.15:0 Idle insert count Counter for number of idle insertions in RX side RO/COR Detailed Description Copyright © 2007–2009, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TLK3134...

  • Page 59: Rx_Ctc_Delete_Count

    BIT(s) NAME DESCRIPTION ACCESS When set, resets XAUI data path but does not reset any R/W registers. 4/5.32800. 15 XAUI datapath reset RW/SC (Default 1’b0) Detailed Description Copyright © 2007–2009, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TLK3134...

  • Page 60: Test_Pattern_Status

    When set, delays the RX data sent to the XGMII interface by one clock cycle. (Default 1’b0) 4/5.32806. 13 Lane 1 phase shift 4/5.32806. 12 Lane 0 phase shift Detailed Description Copyright © 2007–2009, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TLK3134...

  • Page 61: Channel_Sync_Control

    01 = Selects Jitter cleaned clock (Selecting the jitter cleaned clock while select the jitter cleaner PLL is disabled is not recommended) 10 = Selects SERDES RX clock 11 = Reserved Detailed Description Copyright © 2007–2009, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TLK3134...

  • Page 62: Programmers Reference

    This bit always reads 1 (1) After reset bit is set to one, it automatically sets itself back to zero on the next MDC clock cycle. Detailed Description Copyright © 2007–2009, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s):...

  • Page 63: Phy_Status_1

    Read will return 0, writes will be ignored. 15.13 1000Base-T FD Read will return 0, writes will be ignored. 15.12 1000Base-T HD Read will return 0, writes will be ignored. Detailed Description Copyright © 2007–2009, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TLK3134...

  • Page 64: Phy_Ch_Control_1

    SERDES transmits MSB first, and the 1000Base-X standard requires LSB to be transmitted first. For standard based operation, the customer may leave this bit alone. (Default 1’b1) Detailed Description Copyright © 2007–2009, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TLK3134...
  • Page 65 0 = Falling edge align mode. Outgoing parallel data is aligned to the falling edge of the parallel output clock Detailed Description Copyright © 2007–2009, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TLK3134...

  • Page 66: Phy_Rx_Ctc_Fifo_Status

    (1) User has to make sure that register 23 is read first and then register 24. If user reads register 24 before reading register 23, then the count value read through register 24 may not be correct. Detailed Description Copyright © 2007–2009, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s):...

  • Page 67: Phy_Crpat_Pattern_Counter_2

    Register 30 (0x1E) (1) This register is not per channel basis. This register can be accessed through any of the 4 channels. Detailed Description Copyright © 2007–2009, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TLK3134...

  • Page 68: 2.10 Top Level Programmers Reference

    10 = Quarter rate (1 data sample/output per 2 PLL output clock cycle) 11 = Reserved (1) These are global PLL control bits and will be applicable to all 4 channels. Detailed Description Copyright © 2007–2009, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TLK3134...
  • Page 69 01 = Half rate (1 data sample/output per PLL output clock cycle) 10 = Quarter rate (1 data sample/output per 2 PLL output clock cycle) 11 = Reserved Detailed Description Copyright © 2007–2009, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TLK3134...

  • Page 70: Serdes_Rx0_Config

    10 = Reserved 11 = Reserved 4/5.36868.1 ENTEST 1= Enables test modes specified in TESTCFG (Register 0x9012) (1) These are SERDES receiver control bits for channel 1. Detailed Description Copyright © 2007–2009, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TLK3134...

  • Page 71: Serdes_Rx2_Config

    10 = Loss of signal detection enabled with threshold in the range of 85-175 mVdfpp. 11 = Reserved. (1) These are SERDES receiver control bits for channel 3. Detailed Description Copyright © 2007–2009, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TLK3134...

  • Page 72: Serdes_Tx0_Config

    1 = Applicable for SWING settings 750 mV or more. 4/5.36876.8 0 = Applicable for SWING settings 625 mV or less. (1) These are SERDES transmitter control bits for channel 1. Detailed Description Copyright © 2007–2009, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TLK3134...

  • Page 73: Serdes_Tx2_Config

    0 = Applicable for SWING settings 625 mV or less. Transmitter Differential output De-emphasis control 4/5.36880.7:4 DE-EMPHASIS Refer Table 2-104: Transmit De-emphasis Control (1) These are SERDES transmitter control bits for channel 3. Detailed Description Copyright © 2007–2009, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TLK3134...

  • Page 74: Transmit De-Emphasis Control

    1 – Enables test pattern generation in SERDES TX macro. (1) Above control bits are only for vendor testing only. Customer should leave them at their default values Detailed Description Copyright © 2007–2009, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s):...
  • Page 75 01 = Clock pattern (Half baud clock pattern with period of 2UI) 10 = 2 - 1 PRBS pattern 11 = 2 – 1 PRBS pattern Detailed Description Copyright © 2007–2009, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TLK3134...

  • Page 76: Serdes_Test_Config_Rx

    When ST = 1, this bit status is valid only when SERDES RX test pattern verification bits are set (1) Above status bits are only for Receive CH 1. Detailed Description Copyright © 2007–2009, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TLK3134...

  • Page 77: Serdes_Rx2_Status

    When HIGH, indicates an error occurred during test pattern verification 4/5.36889.0 TX CH 2 TESTFAIL for SERDES TX CH 2. (1) Above status bits are only for Transmit CH 2. Detailed Description Copyright © 2007–2009, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TLK3134...

  • Page 78: Serdes_Tx3_Status

    01 = Selects recovered clock as HSTL VTP 2x clock divider input 10 = Selects CMOS REFCLK as HSTL VTP 2x clock divider input 11 = Selects differential REFCLKP/N as HSTL VTP 2x clock divider input Detailed Description Copyright © 2007–2009, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TLK3134...

  • Page 79: Jc_Vtp_Clk_Div_Control

    (Example: To program REF_DIV to decimal value 4, 14:8 needs to be set to 7’b0010000) 1 = Enables Feedback divider 4/5.37124.7 FBDIV_EN 0 = Disables feedback divider Detailed Description Copyright © 2007–2009, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TLK3134...

  • Page 80: Jc_Rxb_Output_Clk_Div_Control

    0x0101 86 - 88 0x02FB 89 - 91 0x0183 92 - 99 0x0237 100 - 107 0x0181 108 - 113 0x0261 114 - 127 0x0215 Detailed Description Copyright © 2007–2009, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TLK3134...

  • Page 81: Jc_Pll_Control

    Enable for TX clock out from SERDES REFCLK MUX. For TI purposes 4/5.37200.3 DIFFTX_ENTST only. Enable for RX clock out from SERDES REFCLK MUX. For TI purposes 4/5.37200.2 DIFFRX_ENTST only. Detailed Description Copyright © 2007–2009, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TLK3134...

  • Page 82: Jc_Ti_Test_Control_2

    Table 2-136. DIE_ID_2 ADDRESS: 0x9205 DEFAULT: 0x0000 BIT(s) NAME DESCRIPTION ACCESS 4/5.37381.15:0 Die ID [47:32] Bits [47:32] of the Die ID. Unique TI DIE identifier. Detailed Description Copyright © 2007–2009, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TLK3134...

  • Page 83: Die_Id_1

    01 = Half termination strength (300 Ω to VHSTL&GND) 10 = 3/4 termination strength (200 Ω to VHSTL&GND) 11 = Full termination strength (150 Ω to VHSTL&GND) Detailed Description Copyright © 2007–2009, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TLK3134...

  • Page 84: Hstl_Output_Slewrate_Control

    3’b110 = Update on 7 consecutive update requests 3’b111 = Update on 8 consecutive update requests Impedance Lock Control 4/5.37634.3 I_LOCK When set, disables dynamic impedance control updates for HSTL input cells Detailed Description Copyright © 2007–2009, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TLK3134...

  • Page 85: Hstl_Output_Vtp_Control

    0 = External voltage reference used for HSTL input signals 4/5.37636.3 VTP POWERSAVE When set, enables power save mode on HSTL VTP controllers 4/5.37636.2 GP 3-state Control When set, 3-states GP outputs Detailed Description Copyright © 2007–2009, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TLK3134...

  • Page 86: Tx0_Dll_Control

    Table 2-154: DLL Offset Control When asserted, the internal filter is used to reduce the cycle to cycle jitter 4/5.37891.3 Filter_en of the output clock. Detailed Description Copyright © 2007–2009, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TLK3134...

  • Page 87: Rx0_Dll_Control

    When asserted, the internal filter is used to reduce the cycle to cycle jitter 4/5.37895.3 Filter_en of the output clock. Table 2-154. DLL Offset Control OFFSET[2:0] VALUE RESULT No delay elements are added Detailed Description Copyright © 2007–2009, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TLK3134...

  • Page 88: Tx0_Dll_Status

    DESCRIPTION ACCESS 4/5.37901.5:0 Delay_status[5:0] For TI use only. Table 2-161. RX2_DLL_STATUS ADDRESS: 0x940E DEFAULT: 0x0000 BIT(s) NAME DESCRIPTION ACCESS 4/5.37902.5:0 Delay_status[5:0] For TI use only. Detailed Description Copyright © 2007–2009, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TLK3134...

  • Page 89: Rx3_Dll_Status

    4/5.38400.15 STCI_CLK Bit to generate STCI clock in functional mode. 4/5.38400.11:10 STCI_CFG[1:0] STCI CFG control 4/5.38400.7 STCI_D STCI data in 4/5.38400.3 STCI_Q STCI read data Detailed Description Copyright © 2007–2009, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TLK3134...

  • Page 90: Testclk_Control

    0 = Uses duty cycle corrected RX/TXBCLK. (Duty cycle set to 50-50, no Bypass phase relationship to SERDES parallel launch and capture clock)(Default) For TI test purposes only Detailed Description Copyright © 2007–2009, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TLK3134...

  • Page 91: Device Reset Requirements/Procedure

    – Wait 50 ms in order for JCPLL to lock – If using clock bypass mode (JCPLL Off) • JCPLL Mux Settings (see Figure 1-3) – Select REFCLK input (Default = Differential) Device Reset Requirements/Procedure Copyright © 2007–2009, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TLK3134...
  • Page 92 – Write 16'h0028 to 4/5.37890 TX2_DLL_CONTROL – Write 16'h0028 to 4/5.37891 TX3_DLL_CONTROL • Poll Serdes PLL Status for Locked State – Read 4/5.36891.4,0 SERDES_PLL_STATUS – PLL_LOCK_TX/RX Device Reset Requirements/Procedure Copyright © 2007–2009, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TLK3134...
  • Page 93 – Read Verify 4/5.24.3:0 XS_LANE_STATUS – Lane (3-0) sync (4’b1111) – Read Verify 4/5.36891.4 SERDES_PLL_STATUS – PLL_LOCK_RX (1’b1) – Read Verify 4/5.36891.0 SERDES_PLL_STATUS – PLL_LOCK_TX (1’b1) Device Reset Requirements/Procedure Copyright © 2007–2009, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TLK3134...

  • Page 94: Gigabit Ethernet Mode (Rgmii)

    – Write 3'b000 to 4/5.37127.14:12 to set control bits for VCO tail current to 0 – Write 1’b1 to 4/5.37127.15 to enable Jitter Cleaner – Wait 50 ms in order for JCPLL to lock Device Reset Requirements/Procedure Copyright © 2007–2009, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TLK3134...
  • Page 95 – Write 1’b1 to 4/5.36880.8 to set channel 3 TX CM bit • RX equalization settings – Write 4’b0001 to 4/5.36866.15:12 to turn on adaptive equalization (4’b0000 is off) Device Reset Requirements/Procedure Copyright © 2007–2009, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TLK3134...
  • Page 96 – Read Verify 28.13:12 PHY_CHANNEL_STATUS – Enc/Dec Invalid Code Word (2’b00) (per channel) – Read Verify 4/5.36891.4 SERDES_PLL_STATUS – PLL_LOCK_RX (1’b1) – Read Verify 4/5.36891.0 SERDES_PLL_STATUS – PLL_LOCK_TX (1’b1) Device Reset Requirements/Procedure Copyright © 2007–2009, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TLK3134...

  • Page 97: Jitter Test Pattern Generation And Verification Procedures

    XAUI Based Mixed Frequency Test Pattern: – Follow the XAUI Based High Frequency Test Pattern procedure above, with the following exception: • Write 2’b10 to 4/5.25.1:0 instead of 2’b00. Device Reset Requirements/Procedure Copyright © 2007–2009, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TLK3134...
  • Page 98 Write 1’b1 to 4/5.32769.0 instead of 4/5.32769.1. • 10GFC Based Continuous Jitter Test Pattern (CJPAT): – Follow the XAUI Based Continuous Random Test Pattern procedure above, with the following Device Reset Requirements/Procedure Copyright © 2007–2009, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TLK3134...
  • Page 99 Read 22.15:0, and verify 16’h0000 is read to confirm error free operation. • 1000Base-X Based Continuous Random Pattern (CRPAT) Long/Short Test Pattern: – Device Pin Setting(s): Device Reset Requirements/Procedure Copyright © 2007–2009, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TLK3134...
  • Page 100 If more than one test is specified results are unpredictable. If another test type is desired, begin at the first step of that procedure. Device Reset Requirements/Procedure Copyright © 2007–2009, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TLK3134...

  • Page 101: Prbs Test Generation And Verification Procedures

    – For PRBS 2 -1- Ensure ST primary input pin is high. – For PRBS 2 -1- Ensure ST primary input pin is low. Device Reset Requirements/Procedure Copyright © 2007–2009, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TLK3134...
  • Page 102 Appendix A for further Jitter Cleaner provisioning details. – PRBS Selection: • For PRBS 2 – Write 2’b10 4/5.36881.1:0. – Write 2’b10 4/5.36882.1:0. • For PRBS 2 Device Reset Requirements/Procedure Copyright © 2007–2009, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TLK3134...
  • Page 103 0/RD × 0 is errored, provided that ST=0. If ST=1, GPO0 does not indicate test failure status. It is acceptable to de-assert ST (ST=0) at this point in the test (if not already de-asserted). Device Reset Requirements/Procedure Copyright © 2007–2009, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s):...

  • Page 104: Signal Pin Description

    A hard or soft reset must be applied after a change of state occurs on this input signal. Speed Selection pins. These pins put all four channels of TLK3134 into one of the three supported (full/half/quarter) channel operation speeds. 00 – All Four Channels in Full Rate mode 01 –...

  • Page 105: Jtag Signals

    (4.xxxxx.x). If PRTAD[0] is a 1, then a DTE device is selected for XAUI/10GFC register accesses (5.xxxxx.x). PRTAD[4:1] selects the Clause 45 port address (TLK3134 must be located on even boundaries since the lowest port address bit determines DTE/PHY, PRTAD[4: N5, N4, N3, 2.5 V LVCMOS...

  • Page 106: Parallel Data Pins

    Receive Data Clocks (XGMII ) These four signals are the parallel (XGMII) RXCLK_[3:0] VDDQ HSTL side output clocks per channel. In XAUI/10GFC mode, RXCLK_1 is used. Output Device Reset Requirements/Procedure Copyright © 2007–2009, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TLK3134...
  • Page 107 RNBI - Lane To Functional Pin Mapping Table 2-13 TBID - Lane To Functional Pin Mapping Table 2-15 NBID - Lane To Functional Pin Mapping Device Reset Requirements/Procedure Copyright © 2007–2009, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TLK3134...

  • Page 108: Efuse_Control

    Also, to monitor PRBS testing real time, these outputs must be available for probing on the application board. Device Reset Requirements/Procedure Copyright © 2007–2009, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TLK3134...

  • Page 109: Voltage Supply And Reference Pins

    SERDES Voltage Regulator Input (1.5 V –or– 1.8 V) P11, P7 VDDT SERDES Termination Voltage (1.2 V) T4, T9 T10, T13, T7 VDDD SERDES Digital Power (1.2 V) U15, U3 Device Reset Requirements/Procedure Copyright © 2007–2009, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TLK3134...

  • Page 110: Jitter Cleaner Related Pins

    AGND AMUX0 VDDD AGND VDDT ENABLE PRBS_EN VDDD TDN1 TDP1 AVDD TDN3 TDP3 AVDD Figure 3-1. Device Pinout Diagram – Part 1 (Top View) Device Reset Requirements/Procedure Copyright © 2007–2009, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TLK3134...

  • Page 111: Device Pinout Diagram - Part 1 (Top View)

    AGND AMUX1 VDDD AGND DGND VDDM RDP1 RDN1 AVDD RDP3 RDN3 VDDD MDIO DGND Figure 3-2. Device Pinout Diagram – Part 2 (Top View) Device Reset Requirements/Procedure Copyright © 2007–2009, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TLK3134...

  • Page 112: Electrical Specifications

    VDDO Shutdown current (2.63V) ENABLE low VDDA_VCO, VDD_PLL, Shutdown current (1.26V) ENABLE low VDD_CML, VDDA_CP (1) Toggle RST_N before setting ENABLE low for proper shutdown. Electrical Specifications Copyright © 2007–2009, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TLK3134...

  • Page 113: Reference Clock Timing Requirements (Refclkp/N)

    VCO Output Jitter (rms) 1.2 MHz → 30 MHz VCO Output Jitter (rms) 600 kHz → 30 MHz 300 kHz → 30 MHz VCO Output Jitter (rms) Electrical Specifications Copyright © 2007–2009, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TLK3134...

  • Page 114: Lvcmos Electrical Characteristics

    High output current –8 OH(dc) Low output current OL(dc) Input Capacitance Tacr AC Test Condition Rise Time (20 → 80%) Tacs AC Test Condition Signal Swing Electrical Specifications Copyright © 2007–2009, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TLK3134...

  • Page 115: 4.10 Serial Transmitter/Receiver Characteristics

    Total delay from TD input to TX Figure 2-20. TBID Mode Bit Times (LATENCY) output (1) Unit Interval = one serial bit time (min. 320 ps) Electrical Specifications Copyright © 2007–2009, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TLK3134...

  • Page 116: 4.11 Parameter Measurement

    0.25 * V OD(pp) 0.25 * V OD(pp) time Figure 4-1. Transmit Output Waveform Parameter Definitions –A1 –A2 1-X2 1-X1 Time (UI) Figure 4-2. Transmit Template Electrical Specifications Copyright © 2007–2009, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TLK3134...

  • Page 117: Transmit Template

    Gaussian random edge jitter distribution at a maximum BER = 10 Figure 4-4. Input Jitter The TLK3134 has several different application modes, which impact parallel interface I/O timing definitions. Each of the modes is defined below, and then subsequently referred to in the detailed timing parameter definitions.

  • Page 118: Parallel Interface - Valid Signal Operational Mode Definitions

    TXCLK = TXCLK_ [2] RXCLK = RXCLK_ [2] -or- -or- TXDATA = TXD_ [27:24] RXDATA = RXD_ [27:24] TXCLK = TXCLK_ [3] RXCLK = RXCLK_ [3] Electrical Specifications Copyright © 2007–2009, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TLK3134...
  • Page 119 CH1: RX Control Bit = RXC_[1] TXCLK = TXCLK_ [3] RXCLK = RXCLK_ [3] CH2: RX Control Bit = RXC_[2] CH3: RX Control Bit = RXC_[3] Electrical Specifications Copyright © 2007–2009, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TLK3134...

  • Page 120: Hstl Output Switching Characteristics (Ddr Timing Mode Only)

    Figure 4-5. HSTL (DDR Timing Mode Only) Source Centered Output Timing Requirements OH(ac) VDDQ/2 RXCLK OL(ac) OH(ac) VDDQ/2 RXDATA OL(ac) Figure 4-6. HSTL (DDR Timing Mode Only) Source Aligned Output Timing Requirements Electrical Specifications Copyright © 2007–2009, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TLK3134...

  • Page 121: Hstl Output Switching Characteristics (Sdr Timing Mode Only)

    Figure 4-7. HSTL (SDR Timing Mode Only) Rising Edge Aligned Output Timing Requirements PERIOD OH(ac) VDDQ/2 RXCLK OL(ac) OH(ac) VDDQ/2 RXDATA OL(ac) Figure 4-8. HSTL (SDR Timing Mode Only) Falling Edge Aligned Output Timing Requirements Electrical Specifications Copyright © 2007–2009, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TLK3134...

  • Page 122: 4.14 Hstl (Ddr Timing Mode Only) Input Timing Requirements

    Figure 4-9. HSTL (DDR Timing Mode Only) Source Centered Data Input Timing Requirements OH(ac) VDDQ/2 TXCLK OL(ac) Tskew Tskew OH(ac) TXDATA VDDQ/2 OL(ac) Figure 4-10. HSTL (DDR Timing Mode Only) Source Aligned Data Input Timing Requirements Electrical Specifications Copyright © 2007–2009, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TLK3134...

  • Page 123: 4.15 Hstl (Sdr Timing Mode Only) Input Timing Requirements

    TXCLK IL(ac) SETUP HOLD IH(ac) TXDATA VDDQ/2 IL(ac) Figure 4-12. HSTL (SDR Timing Mode Only) Rising Edge Aligned (Falling Edge Sampled) Data Input Timing Requirements Electrical Specifications Copyright © 2007–2009, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TLK3134...

  • Page 124: 4.16 Mdio Timing Requirements Over Recommended Operating Conditions

    HOLD MDIO Figure 4-13. MDIO Read/Write Timing VDDQ 150/200/ 300/Open 50 W transmission line 150/200/ 300/Open VDDQ VREF INPUT OUTPUT Figure 4-14. HSTL I/O Schematic Electrical Specifications Copyright © 2007–2009, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TLK3134...

  • Page 125: 4.17 Jtag Timing Requirements Over Recommended Operating Conditions

    Figure 4-15. hold TDO delay from TCK falling Figure 4-15. valid (1) Unless otherwise noted. PERIOD SETUP HOLD TDI/TMS/ TRST_N VALID Figure 4-15. JTAG Timing Electrical Specifications Copyright © 2007–2009, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TLK3134...

  • Page 126: Jtag Timing

    1.6 à 3.2 Gbps 9 Bit SERDES Mode 3.2 à 3.75 Gbps Latency measurement only operates in TBI, TBID, and RTBI modes. Figure 4-16. TLK3134 Application Mode vs Interface Timing Mode Support Electrical Specifications Copyright © 2007–2009, Texas Instruments Incorporated Submit Documentation Feedback...

  • Page 127: Package Dissipation Rating

    Junction to free air thermal resistance Airflow = 0 lfpm 14.45 °C/W θ Junction to free air thermal resistance Airflow = 150 lfpm 7.50 °C/W Electrical Specifications Copyright © 2007–2009, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TLK3134...

  • Page 128: Worst Case Device Power Dissipation

    None Max. None Max. None Max. Termination Total Power (mW) 1078 1490 1178 1591 1264 1845 1366 1947 Figure 4-18. Worst Case Device Power Dissipation Electrical Specifications Copyright © 2007–2009, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TLK3134...

  • Page 129: Appendix A - Frequency Ranges Supported

    The following tables show the details of REFCLK input frequency versus Jitter Cleaner PLL multiplier value for each application TLK3134 supports. If the desired serial bit rate is between 2.0 Gbps and 3.75 Gbps, full rate should be selected for the RATE[1:0] bits for that channel.

  • Page 130: Reference Clock Selection - Xaui - 10 Gbe Mode

    250.00000 125.00000 2500.000 1250.000 625.000 250.00000 250.00000 2500.000 1250.000 625.000 250.00000 500.00000 Figure A-3. Reference Clock Selection – Gigabit Ethernet Mode APPENDIX A – Frequency Ranges Supported Copyright © 2007–2009, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TLK3134...

  • Page 131: Reference Clock Selection - Gigabit Ethernet Mode

    768.000 307.20000 153.60000 3072.000 1536.000 768.000 307.20000 307.20000 3072.000 1536.000 768.000 307.20000 614.40000 Figure A-5. Reference Clock Selection – OBSAI Mode APPENDIX A – Frequency Ranges Supported Copyright © 2007–2009, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TLK3134...

  • Page 132: Reference Clock Selection - Obsai Mode

    46.8750 50.0000 93.7500 2000.00 3750.00 Figure A-7. Reference Clock Selection – 9/10 Bit SERDES Mode – Full Rate (SPEED[1:0] == 00) APPENDIX A – Frequency Ranges Supported Copyright © 2007–2009, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TLK3134...

  • Page 133: Reference Clock Selection - 9/10 Bit Serdes Mode - Full Rate (Speed[1:0] == 00)

    25.0000 53.1250 50.0000 106.2500 500.00 1062.50 Figure A-9. Reference Clock Selection –9/10 Bit SERDES Mode – Quarter Rate (SPEED[1:0] == 10) APPENDIX A – Frequency Ranges Supported Copyright © 2007–2009, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TLK3134...

  • Page 134: Reference Clock Selection -9/10 Bit Serdes Mode - Quarter Rate (Speed[1:0] == 10)

    100.0000 125.0000 200.0000 1000.00 1600.00 Figure A-11. Reference Clock Selection – 8 Bit SERDES Mode – Half Rate (SPEED[1:0] == 01) APPENDIX A – Frequency Ranges Supported Copyright © 2007–2009, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TLK3134...

  • Page 135: Reference Clock Selection - 8 Bit Serdes Mode - Half Rate (Speed[1:0] == 01)

    100.0000 150.0000 200.0000 600.00 800.00 Figure A-12. Reference Clock Selection – 8 Bit SERDES Mode – Quarter Rate (SPEED[1:0] == 10) APPENDIX A – Frequency Ranges Supported Copyright © 2007–2009, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TLK3134...

  • Page 136: Reference Clock Selection - 8 Bit Serdes Mode - Quarter Rate (Speed[1:0] == 10)

    TLK3134 SLLS838F – MAY 2007 – REVISED DECEMBER 2009 www.ti.com Figure A-13. Standard Based Jitter Cleaner/SERDES Provisioning APPENDIX A – Frequency Ranges Supported Copyright © 2007–2009, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TLK3134...

  • Page 137: Standard Based Jitter Cleaner/Serdes Provisioning

    Note that REFCLK is limited to 93.75 Mhz when in full rate mode to achieve 3750 Mbps serial data rate. Figure A-14. 9/10 BIT SERDES Mode – Jitter Cleaner/SERDES (2x) Provisioning APPENDIX A – Frequency Ranges Supported Copyright © 2007–2009, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s):...

  • Page 138: 9/10 Bit Serdes Mode - Jitter Cleaner/Serdes (2X) Provisioning

    Note that REFCLK is limited to 187.5 Mhz when in full rate mode to achieve 3750 Mbps serial data rate. Figure A-15. 9/10 BIT SERDES Mode – Jitter Cleaner/SERDES (1x) Provisioning APPENDIX A – Frequency Ranges Supported Copyright © 2007–2009, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s):...

  • Page 139: 9/10 Bit Serdes Mode - Jitter Cleaner/Serdes (1X) Provisioning

    Note 2: RATE[1:0] bits are found in the SERDES_RATE_CONFIG_TX_RX register at address 4/5.36865. Figure A-16. 9/10 BIT SERDES Mode – Jitter Cleaner/SERDES (0.5x) Provisioning APPENDIX A – Frequency Ranges Supported Copyright © 2007–2009, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s):...

  • Page 140: 9/10 Bit Serdes Mode - Jitter Cleaner/Serdes (0.5X) Provisioning

    Note 2: RATE[1:0] bits are found in the SERDES_RATE_CONFIG_TX_RX register at address 4/5.36865. Figure A-17. 9/10 BIT SERDES Mode – Jitter Cleaner/SERDES (0.25x) Provisioning APPENDIX A – Frequency Ranges Supported Copyright © 2007–2009, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s):...

  • Page 141: 9/10 Bit Serdes Mode - Jitter Cleaner/Serdes (0.25X) Provisioning

    Note that REFCLK is limited to 93.75 Mhz when in Full rate mode to achieve 3000 Mbps serial data rate. Figure A-18. 8 BIT SERDES Mode – Jitter Cleaner/SERDES (2x) Provisioning APPENDIX A – Frequency Ranges Supported Copyright © 2007–2009, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s):...

  • Page 142: Bit Serdes Mode - Jitter Cleaner/Serdes (2X) Provisioning

    Note that REFCLK is limited to 187.5 Mhz when in Full rate mode to achieve 3000 Mbps serial data rate. Figure A-19. 8 BIT SERDES Mode – Jitter Cleaner/SERDES (1x) Provisioning APPENDIX A – Frequency Ranges Supported Copyright © 2007–2009, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s):...
  • Page 143 TLK3134 www.ti.com SLLS838F – MAY 2007 – REVISED DECEMBER 2009 Figure A-20. 8 BIT SERDES Mode – Jitter Cleaner/SERDES (0.5x) Provisioning APPENDIX A – Frequency Ranges Supported Copyright © 2007–2009, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TLK3134...

  • Page 144: Recovered Byte Clock Jitter Cleaner Mode

    SERDES output byte clock and the parallel interface output recovered byte clock. Depending upon the selection of TX_SEL, it may also be necessary to provision RXTX_DIV with the same value as RXB_DIV. APPENDIX A – Frequency Ranges Supported Copyright © 2007–2009, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TLK3134...

  • Page 145: Recovered Byte Clock Jitter Cleaner Mode

    223.2143 225.0000 240.3846 243.7500 260.4167 265.9091 284.0909 292.5000 312.5000 325.0000 347.2222 365.6250 375.0000 Figure A-21. Recovered Byte Clock Jitter Cleaner Mode APPENDIX A – Frequency Ranges Supported Copyright © 2007–2009, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TLK3134...

  • Page 146: Appendix B - Jitter Cleaner Pll External Loop Filter

    C1=3.3uF VSSA_VCO VSSA_VCO External passive loop filter External passive loop filter Figure B-1. Jitter Cleaner External Loop Filter APPENDIX B – Jitter Cleaner PLL External Loop Filter Copyright © 2007–2009, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TLK3134...

  • Page 147: Appendix C - Device Test Mode

    TEST_DOUT2 Scan Out 2 STCI_Q GPO3 TEST_DOUT3 Scan Out 1 EFUSE_TDO TEST_DOUT4 or JC PLL GPO4 Burnin_Output Burnin_Output Digital Test Out APPENDIX C – Device Test Mode Copyright © 2007–2009, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TLK3134...
  • Page 148 Green (RoHS Call TI | SNAGCU Level-4-260C-72 HR -40 to 85 TLK3134 & no Sb/Br) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
  • Page 149 PACKAGE OPTION ADDENDUM www.ti.com 29-Apr-2014 Addendum-Page 2...

  • Page 151: Important Notice

    IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue.

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