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Eight Bit SERDES Mode - Clock Range Support (RATE[1:0] == 10) (Quarter)
REFCLK
Minimum Maximum
(MHz)
300.0000 375.0000
150.0000 265.6250
######## ########
500.0000 937.5000
500.0000 750.0000
300.0000 375.0000
300.0000 375.0000
150.0000 200.0000
150.0000 187.5000
75.0000
Figure A-12. Reference Clock Selection – 8 Bit SERDES Mode – Quarter Rate (SPEED[1:0] == 10)
Copyright © 2007–2009, Texas Instruments Incorporated
Jitter
SERDES REFCLK
Cleaner
Minimum Maximum
(MHz)
Multiplier
(MHz)
OFF
300.0000 375.0000
OFF
150.0000 265.6250
0.25
250.0000 375.0000
0.25
125.0000 234.3750
0.5
250.0000 375.0000
0.5
150.0000 187.5000
1
300.0000 375.0000
1
150.0000 200.0000
2
300.0000 375.0000
100.0000
2
150.0000 200.0000
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Product Folder Link(s):
SLLS838F – MAY 2007 – REVISED DECEMBER 2009
SERDES
Serial Data Rate (Mbps)
PLL
Quarter
(MHz)
Multiplier Minimum Maximum
4
600.00
8
600.00
4
500.00
8
500.00
4
500.00
8
600.00
4
600.00
8
600.00
4
600.00
8
600.00
APPENDIX A – Frequency Ranges Supported
TLK3134
TLK3134
750.00
1062.50
750.00
937.50
750.00
750.00
750.00
800.00
750.00
800.00
135
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