Parallel Data Pins - Texas Instruments TLK3134 Data Manual

TLK3134
SLLS838F – MAY 2007 – REVISED DECEMBER 2009
SIGNAL LOCATION VOLTAGE
ST M5
REFCLK M2
SIGNAL LOCATION
C11
F16
TXCLK_[3:0]
K13
M14
B11
A13
B13
C12
E12
B14
D13
C15
D14
E13
B16
D15
F13
C16
D17
E15
TXD_[31:0]
E16
E17
F15
G16
G13
G17
J13
J14
J15
J17
K15
M17
L16
L13
L14
M16
B12
D12
A16
C17
TXC_[7:0]
F14
H16
K17
L15
C2
C6
RXCLK_[3:0]
D7
D9
106 Device Reset Requirements/Procedure
Table 3-3. MDIO Related Signals (continued)
TYPE
2.5 V LVCMOS
VDDO
Input
2.5 V LVCMOS
VDDO
Input
Table 3-4. Parallel Data Pins
VOLTAGE TYPE
1.5/1.8 V
VDDQ/ VREF1/2
HSTL Input side input clocks per channel. In XAUI/10GFC mode, TXCLK_1 is used.
1.5/1.8 V
VDDQ/ VREF1/2
HSTL Input
1.5/1.8 V
VDDQ/ VREF1/2
HSTL Input
1.5/1.8 V
VDDQ HSTL
Output
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MDIO Select Used to select Clause 22 (=1) or Clause 45 (=0) operation.
A hard or soft reset must be applied after a change of state occurs on this
input signal.
Single Ended Reference Clock Single ended reference clock input. By
default, the differential reference clock (REFCLKP/N) is selected. This default
value may be changed by a mdio register (4/5.37120.15:14). The acceptable
input frequency range on this input signal is 50 Mhz → 150 Mhz.
Jitter performance is optimal when using the differential REFCLK input.
Transmit Data Clocks (XGMII) These four signals are the parallel (XGMII)
Transmit Data Pins (XGMII) Parallel interface data pins.
See the following tables for functionality per application mode:
Table 2-3 XAUI - Lane To Functional Pin Mapping (XAUI_ORDER = 1)
Table 2-4 10GFC - Lane To Functional Pin Mapping (XAUI_ORDER = 0)
Table 2-5 RGMII - Lane To Functional Pin Mapping
Table 2-6 RTBI - Lane To Functional Pin Mapping
Table 2-7 TBI - Lane To Functional Pin Mapping
Table 2-8 GMII - Lane To Functional Pin Mapping
Table 2-9 EBI - Lane To Functional Pin Mapping
Table 2-10 REBI - Lane To Functional Pin Mapping
Table 2-11 NBI - Lane To Functional Pin Mapping
Table 2-12 RNBI - Lane To Functional Pin Mapping
Table 2-13 TBID - Lane To Functional Pin Mapping
Table 2-15 NBID - Lane To Functional Pin Mapping
See the following tables for functionality per application mode:
Table 2-3 XAUI - Lane To Functional Pin Mapping (XAUI_ORDER = 1)
Table 2-4 10GFC - Lane To Functional Pin Mapping (XAUI_ORDER = 0)
Table 2-5 RGMII - Lane To Functional Pin Mapping
Table 2-6 RTBI - Lane To Functional Pin Mapping
Table 2-7 TBI - Lane To Functional Pin Mapping
Table 2-8 GMII - Lane To Functional Pin Mapping
Table 2-9 EBI - Lane To Functional Pin Mapping
Table 2-10 REBI - Lane To Functional Pin Mapping
Table 2-11 NBI - Lane To Functional Pin Mapping
Table 2-12 RNBI - Lane To Functional Pin Mapping
Table 2-13 TBID - Lane To Functional Pin Mapping
Table 2-15 NBID - Lane To Functional Pin Mapping
Receive Data Clocks (XGMII ) These four signals are the parallel (XGMII)
side output clocks per channel. In XAUI/10GFC mode, RXCLK_1 is used.
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TLK3134
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