Nbid Mode (Nine Bit Interface Ddr); Nbid - Individual Channel Byte Ordering - Channel 0 Example; Nbid - Lane To Functional Pin Mapping - Texas Instruments TLK3134 Data Manual

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2.7.11 NBID Mode (Nine Bit Interface DDR)

DATA CHANNEL TRANSMIT DATA 9 BITS
NUMBER
Channel 0
Channel 1 {TXC_[1],TXD_[15:8]}
Channel 2 {TXC_[2],TXD_[23:16]}
Channel 3 {TXC_[3],TXD_[31:24]}
Figure 2-17. NBID – Individual Channel Byte Ordering – Channel 0 Example
Copyright © 2007–2009, Texas Instruments Incorporated
Table 2-14. NBID – Lane To Functional Pin Mapping
RECEIVE DATA 9 BITS
(INPUT)
{TXC_[0],TXD_[7:0]}
{RXC_[1],RXD_[15:8]}
{RXC_[2],RXD_[23:16]}
{RXC_[3],RXD_[31:24]}
TXCLK_[0]
Data0[8:0] = {Control
TXC_[0], TXD_[7:0]
RXCLK_[0]
Data0[8:0] = {Control
RXC_[0], RXD_[7:0]
TXCLK_[0]
Data0[8:0] = {Control
TXC_[0], TXD_[7:0]
RXCLK_[0]
Data0[8:0] = {Control
RXC_[0], RXD_[7:0]
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(OUTPUT)
{RXC_[0],RXD_[7:0]}
DDR Source Centered Timing
Data1[8:0] = {Control
Bit, Data Byte} Bit, Data Byte}
Data1[8:0] = {Control
Bit, Data Byte} Bit, Data Byte}
DDR Source Aligned Timing
Data1[8:0] = {Control
Bit, Data Byte} Bit, Data Byte}
Data1[8:0] = {Control
Bit, Data Byte} Bit, Data Byte}
TLK3134
SLLS838F – MAY 2007 – REVISED DECEMBER 2009
TRANSMIT CLOCK RECEIVE CLOCK
(INPUT)
TXCLK_[0]
TXCLK_[1]
TXCLK_[2]
TXCLK_[3]
Detailed Description
TLK3134
(OUTPUT)
RXCLK_ [0]
RXCLK_ [1]
RXCLK_ [2]
RXCLK_ [3]
31