2.7.15 Channel Clock To Serial Transmit Clock Synchronization; 2.7.16 Data Reception Latency; 2.7.17 8B/10B Encoder; Transmission Latency - Texas Instruments TLK3134 Data Manual

4-channel multi-rate transceiver
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TLK3134
SLLS838F – MAY 2007 – REVISED DECEMBER 2009
TXxP
TXxN
TXD[31: ] 0
TCLK

2.7.15 Channel Clock to Serial Transmit Clock Synchronization

In XAUI mode, the TLK3134 allows ±200 ppm difference between the serdes transmit reference on the
XAUI side, versus the input TCLK on the XGMII side. There exists a FIFO capable of CTC operations, and
has a depth of 32 locations (32 bits wide per location).
The reference clock and the transmit data clock(s) may be from a common source, but the design allows
for up to ±200 ppm of frequency difference should the application require it.
Note that there are no CTC operations in any of the independent channel modes.

2.7.16 Data Reception Latency

For each serial link, the serial-to-parallel data latency is the time from when the first bit arrives at the serial
receiver input until it is output in the aligned parallel word on the XGMII, as shown in
maximum receive latency is a function of the mode of operation, and is detailed in
Transmitter/Receiver characteristics.
10-Bit Code Received
RDP, RDN
RXD[31:0]
RCLK

2.7.17 8B/10B Encoder

All true serial interfaces require a method of encoding to insure sufficient transition density for the
receiving PLL to acquire and maintain lock. The encoding scheme also maintains the signal DC balance
by keeping the number of ones and zeros balanced which allows for AC coupled data transmission. The
TLK3134 uses the 8B/10B encoding algorithm that is used by 10Gbps and 1Gbps Ethernet and
FibreChannel standards. This provides good transition density for clock recovery and improves error
checking. The TLK3134 will internally encode and decode the data such that the user reads and writes
actual 8-bit data on each channel. The encoder and decoder functions can optionally be enabled or
disabled on a per channel basis.
34
Detailed Description
T latency
Bytes to Be
Transmitted
Figure 2-20. Transmission Latency
NOTE
R latency
Figure 2-21. Receiver Latency
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TLK3134
10-Bit Code
Transmitted
Figure
Section
Bytes Received
Copyright © 2007–2009, Texas Instruments Incorporated
www.ti.com
2-21. The
4.10: Serial

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