Parallel Interface - Valid Signal Operational Mode Definitions - Texas Instruments TLK3134 Data Manual

TLK3134
SLLS838F – MAY 2007 – REVISED DECEMBER 2009
Table 4-2. Parallel Interface – Valid Signal Operational Mode Definitions
TIMING
MODE
NAME
XAUI Applications, 10 Gigabit Fibre Channel Applications.
Only DDR Timing Supported
XGMII See Section 4.12: HSTL Output Switching Characteristics (DDR Timing
Mode Only) and Section 4.14: HSTL (DDR Timing Mode Only) Input Timing
Requirements for AC timing details.
1000Base-X Applications Reduced Ten Bit Applications (RTBI)
Only DDR Timing Supported
See Section 4.12: HSTL Output Switching Characteristics (DDR Timing
Mode Only) and Section 4.14: HSTL (DDR Timing Mode Only) Input Timing
Requirements for AC timing details.
Note: In RGMII Mode
CH0: TX_EN/TX_ER = TXD_[4]
RGMII, RTBI
CH1: TX_EN/TX_ER = TXD_[12]
CH2: TX_EN/TX_ER = TXD_[20]
CH3: TX_EN/TX_ER = TXD_[28]
CH0: RX_DV/RX_ER = RXD_[4]
CH1: RX_DV/RX_ER = RXD_[12]
CH2: RX_DV/RX_ER = RXD_[20]
CH3: RX_DV/RX_ER = RXD_[28]
Ten Bit Interface Mode (TBI)
Only SDR Timing Supported
See Section 4.13: HSTL Output Switching Characteristics (SDR Timing
Mode Only) and Section 4.15: HSTL (SDR Timing Mode Only) Input Timing
Requirements for AC timing details.
Note: In GMII Mode
CH0: TX_EN = TXC_[0]
CH1: TX_EN = TXC_[1]
CH2: TX_EN = TXC_[2]
CH3: TX_EN = TXC_[3]
CH0: TX_ER = TXC_[4]
CH1: TX_ER = TXC_[5]
CH2: TX_ER = TXC_[6]
CH3: TX_ER = TXC_[7]
CH0: RX_DV = RXC_[0]
CH1: RX_DV = RXC_[1]
CH2: RX_DV = RXC_[2]
CH3: RX_DV = RXC_[3]
CH0: RX_ER = RXC_[4]
TBI, GMII
CH1: RX_ER = RXC_[5]
CH2: RX_ER = RXC_[6]
CH3: RX_ER = RXC_[7]
Note: In TBI Mode
CH0: TX Data Bit 8 = TXC_[0]
CH1: TX Data Bit 8 = TXC_[1]
CH2: TX Data Bit 8 = TXC_[2]
CH3: TX Data Bit 8 = TXC_[3] CH0: TX Data Bit 9 = TXC_[4]
CH1: TX Data Bit 9 = TXC_[5]
CH2: TX Data Bit 9 = TXC_[6]
CH3: TX Data Bit 9 = TXC_[7]
CH0: RX Data Bit 8 = RXC_[0]
CH1: RX Data Bit 8 = RXC_[1]
CH2: RX Data Bit 8 = RXC_[2]
CH3: RX Data Bit 8 = RXC_[3]
CH0: RX Data Bit 9 = RXC_[4]
CH1: RX Data Bit 9 = RXC_[5]
CH2: RX Data Bit 9 = RXC_[6]
CH3: RX Data Bit 9 = RXC_[7]
Eight Bit Interface Mode (EBI)
SDR Timing Support
EBI See Section 4.13: HSTL Output Switching Characteristics (SDR Timing
Mode Only) and Section 4.15: HSTL (SDR Timing Mode Only) Input Timing
Requirements for AC timing details.
Reduced Eight Bit Interface Mode (REBI)
DDR Timing Support
REBI See Section 4.12: HSTL Output Switching Characteristics (DDR Timing
Mode Only) and Section 4.14: HSTL (DDR Timing Mode Only) Input Timing
Requirements for AC timing details.
118 Electrical Specifications
USAGE MODE
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Product Folder Link(s):
TX SIGNALS USED
TXDATA = TXD_[31:0] and TXC_[3:0].
TXCLK = TXCLK_[1].
TXDATA = TXD_[4:0]
TXCLK = TXCLK_[0]
-or-
TXDATA = TXD_[12:8]
TXCLK = TXCLK_ [1]
-or-
TXDATA = TXD_ [20:16]
TXCLK = TXCLK_ [2]
-or-
TXDATA = TXD_ [28:24]
TXCLK = TXCLK_ [3]
TXDATA = TXC_ [4],TXC_ [0],
TXD[7:0]
TXCLK = TXCLK_ [0]
-or-
TXDATA = TXC_ [5],TXC_ [1],
TXD_ [15:8]
TXCLK = TXCLK_ [1]
-or-
TXDATA = TXC_ [6],TXC_ [2],
TXD_ [23:16]
TXCLK = TXCLK_ [2]
-or-
TXDATA = TXC_ [7],TXC_ [3],
TXD_ [31:24]
TXCLK = TXCLK_ [3]
TXDATA = TXD_ [7:0]
TXCLK = TXCLK_ [0]
-or-
TXDATA = TXD_ [15:8]
TXCLK = TXCLK_ [1]
-or-
TXDATA = TXD_ [23:16]
TXCLK = TXCLK_ [2]
-or-
TXDATA = TXD_ [31:24]
TXCLK = TXCLK_ [3]
TXDATA = TXD_ [3:0]
TXCLK = TXCLK_ [0]
-or-
TXDATA = TXD_ [11:8]
TXCLK = TXCLK_ [1]
-or-
TXDATA = TXD_ [19:16]
TXCLK = TXCLK_ [2]
-or-
TXDATA = TXD_ [27:24]
TXCLK = TXCLK_ [3]
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TLK3134
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RX SIGNALS USED
RXDATA = RXD_[31:0] and RXC_[3:0].
RXCLK = RXCLK_[1].
RXDATA = RXD_[4:0]
RXCLK = RXCLK_[0]
-or-
RXDATA = RXD_ [12:8]
RXCLK = RXCLK_ [1]
-or-
RXDATA = RXD_ [20:16]
RXCLK = RXCLK_ [2]
-or-
RXDATA = RXD_ [28:24]
RXCLK = RXCLK_ [3]
RXDATA = RXC_ [4],RXC_ [0],
RXD[7:0]
RXCLK = RXCLK_ [0]
-or-
RXDATA = RXC_ [5],RXC_ [1],
RXD_ [15:8]
RXCLK = RXCLK_ [1]
-or-
RXDATA = RXC_ [6],RXC_ [2],
RXD_ [23:16]
RXCLK = RXCLK_ [2]
-or-
RXDATA = RXC_ [7],RXC_ [3],
RXD_ [31:24]
RXCLK = RXCLK_ [3]
RXDATA = RXD_ [7:0]
RXCLK = RXCLK_ [0]
-or-
RXDATA = RXD_ [15:8]
RXCLK = RXCLK_ [1]
-or-
RXDATA = RXD_ [23:16]
RXCLK = RXCLK_ [2]
-or-
RXDATA = RXD_ [31:24]
RXCLK = RXCLK_ [3]
RXDATA = RXD_ [3:0]
RXCLK = RXCLK_ [0]
-or-
RXDATA = RXD_ [11:8]
RXCLK = RXCLK_ [1]
-or-
RXDATA = RXD_ [19:16]
RXCLK = RXCLK_ [2]
-or-
RXDATA = RXD_ [27:24]
RXCLK = RXCLK_ [3]