Jitter Cleaner Related Pins - Texas Instruments TLK3134 Data Manual

TLK3134
SLLS838F – MAY 2007 – REVISED DECEMBER 2009
SIGNAL LOCATION
REFCLKP/ L1
REFCLKN K1
VDDA_VCO K2
VSSA_VCO K3
VDDA_CP L4
VSSA_CP L5
VDD_CML M1
VSS_CML J1
VDD_PLL J5
VSS_PLL J4
VCO_TL_TST J3
TST_OUT J2
CP_OUT K5
VTUNE K4
1
A DGND
B RXD_19
C VDDQ
D VDDQ
E RXD_23
F RXD_26
G VDDQ
H RXD_30
J VSS_CML TST_OUT
K REFCLKN
L REFCLKP
M VDD_CML REFCLK
N GPO0
P RST_N
R VDDO
T PRTAD0
U ENABLE PRBS_EN
110 Device Reset Requirements/Procedure
Table 3-8. Jitter Cleaner Related Pins
VOLTAGE TYPE
VDD_CML I
P P
G G
P P
G G
P P
G G
P P
G G
G Analog Input
Analog
VDD_PLL
Input/Output
VDDA_CP Analog Output
VDDA_VCO Analog Input
2 3
VDDQ RXD_15 RXD_11
RXD_17 RXD_14 RXD_12
RXCLK_3 DGND RES1
RXD_21 RXC_5 RXD_18
RXD_24 RXD_22 VDDQ
DGND VDDQ RXC_6
RES2 RXD_28 RXD_27
RXD_31 VDDQ RXC_7
VSS_PLL VDD_PLL
VCO_TL_TST
VTUNE
VDDA_VCO VSSA_VCO
VDDO GPO1 VDDA_CP
CODE DGND
PRTAD1 PRTAD2 PRTAD3
DGND VDDO AGND
GPI1 TDP0 TDN0
DVDD AGND VDDT
VDDD TDN1
Figure 3-1. Device Pinout Diagram – Part 1 (Top View)
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Differential Reference Clock Inputs
By default, the differential reference clock (REFCLKP/N) is selected.
This default value may be changed by a mdio register (4/5.37120.15:14).
Must Be Externally AC Coupled
REFCLKP – DPECL REFCLK P Input
REFCLKN – DPECL REFCLK N Input Acceptable input frequency range is
50 MHz → 375 MHz. Jitter performance is optimal when using the
differential REFCLK input.
Jitter Cleaner – VCO Supply - 1.2 V
Jitter Cleaner Ground
Jitter Cleaner – Charge Pump - 1.2 V
Jitter Cleaner Ground
Jitter Cleaner – REFCLKP/N Input Supply - 1.2 V
Jitter Cleaner Ground
Jitter Cleaner Digital Power (1.2 V)
Jitter Cleaner Ground
VCO Testability Input. This signal should be grounded in the application.
Jitter Cleaner Testability Pin. This signal should be left open
(unconnected) in the application.
Charge Pump Output. If the internal Jitter Cleaner PLL is used, this signal
should be connected to the input of the external loop filter (See
Figure B-1). If the internal Jitter Cleaner PLL is not used, this node should
be left open (unconnected).
LC VCO Bias Voltage. This signal should be connected to the output of
the external loop filter if the Jitter Cleaner PLL is used
internal Jitter Cleaner PLL is not used, this node should be grounded.
4 5 6
VDDQ RXD_9
VDDQ RXD_10
RXD_13 RXCLK_2
RXC_4 DGND
RXD_20 RXD_16
RXD_25 DVDD
DGND DVDD
RXD_29 VDDQ
GPO4
CP_OUT GPO3
VSSA_CP GPO2
ST TESTEN
PRTAD4 DVDD
AGND AGND
AVDD TDP2
AGND AMUX0
TDP1 AVDD
Copyright © 2007–2009, Texas Instruments Incorporated
TLK3134
DESCRIPTION
(Figure
7 8 9
DGND RXD_8 VDDQ
RXC_2 RXD_7 RXD_5
VDDQ VDDQ RXD_3
RXCLK_1 RXD_6 RXCLK_0
RXC_3 RXC_1 DGND
VDDQ DVDD DVDD
DGND DGND DGND
DGND DGND DGND
DVDD DGND DGND
DGND DGND DGND
DGND DGND DGND
DGND DGND DGND
AVDD DVDD VDDO
VDDT AGND VDDR
TDN2 AVDD RDN0
VDDD AGND VDDT
TDN3 TDP3 AVDD
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B-1). If the