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TLK3134
SLLS838F – MAY 2007 – REVISED DECEMBER 2009
REF_SEL[1:0]
REFCLK_P
REFCLK_N
REFCLK
RXBCLK[0]
HSTL Output
HSTL_2X_CLK
Divider
HSTL_DIV2[6:0]
2
Detailed Description
2.1
Clocking Modes
The TLK3134 contains an internal low-bandwidth, low-jitter high quality LC oscillator that may be
configured as a jitter cleaner. The jitter cleaner oscillator has a high frequency narrow band of operation
that may be used to generate all common reference clock frequencies by way of programmable pre-scaler
and post-scaler registers. In this manner a poor quality input reference clock can be input to the jitter
cleaner which will lock to the reference clock and provide a clean reference to the internal SERDES PLLs.
Appendix A defines in detail the clocking possibilities, and device settings.
Alternatively, the jitter cleaner may be used to lock to a recovered byte clock from RX channel 0 and
remove jitter that may have transferred through the clock/data recovery circuit from the serial data stream
to the recovered byte clock (including parallel output data timing). In this way the recovered byte clock
may be extracted from the serial data stream yet be suitable for use in applications that require a clean
clock source derived from the serial data stream. The TLK3134 jitter cleaner may only be used on the
recovered byte clock from Channel 0. If the jitter cleaner is used to clean the recovered byte clock, it may
not be used to clean the input reference clock, and the PLL at the center of the deserializer core must
have a clean low-jitter reference clock from an external clock source, preferably a low-jitter crystal based
oscillator. Note that the Transmit SERDES macro can run from the cleaned recovered RX channel 0 byte
clock which allows for the outgoing TX serial data rate for all channels to exactly match the incoming data
rate of RX Channel 0.
The TLK3134 clocking architecture allows for bypass of the Jitter cleaner PLL in cases where power or
application board area is critical.
See
Figure 1-3
Clocking Architecture for a representation of the use of the jitter cleaner in the TLK3134.
14
Detailed Description
00
REFCLK
Jitter Cleaner
01
Divider
PLL Core
REF_DIV[6:0]
1X
Feedback
FB_DIV[6:0]
00
Second PLL
RXBYTE_CLK
01
Output
Divider
10
RXB_DIV[6:0]
11
RXB_SEL[1:0]
Third PLL
00
DELAY_CLK
Output
01
Divider
10
DEL_DIV[6:0]
11
DEL_SEL[1:0]
Fourth PLL
00
Output
01
Divider
10
HSTL_DIV1[6:0]
11
HSTL_SEL[1:0]
Figure 1-3. Block Diagram – TLK3134 Clocking Architecture
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Product Folder Link(s):
First PLL Output
Divider
RXTX_DIV[6:0]
PLL
Divider
RX_SEL[1:0]
(2.875 Ghz Min., 3 Ghz Typ., 3.125 Ghz Max.)
Note: Default Mux Selects Are Underlined.
Copyright © 2007–2009, Texas Instruments Incorporated
TLK3134
TX_SEL[1:0]
SERDES TX
P2S
00
P2S
01
REFCLK_TX
PLL
P2S
10
P2S
11
SERDES RX
S2P
00
S2P
01
REFCLK_RX
PLL
S2P
10
S2P
11
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TX3P/N
TX2P/N
TX1P/N
TX0P/N
RX3P/N
RX2P/N
RX1P/N
RX0P/N
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