Gmii Mode (Gigabit Media Independent Interface); Gmii - Individual Channel Byte Ordering - Channel 0 Example; Gmii - Lane To Functional Pin Mapping - Texas Instruments TLK3134 Data Manual

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2.7.5 GMII Mode (Gigabit Media Independent Interface)

TX_EN
DATA
CONTROL
CHANNEL
BIT
NUMBER
(INPUT)
Channel 0 TXC_[0]
Channel 1 TXC_[1]
Channel 2 TXC_[2]
Channel 3 TXC_[3]
TXC_[0],TXC_[4],TXD_[7:0]
RXC_[0],RXC_[4],RXD_[7:0]
TXC_[0],TXC_[4],TXD_[7:0]
RXC_[0],RXC_[4],RXD_[7:0]
Figure 2-11. GMII – Individual Channel Byte Ordering – Channel 0 Example
Copyright © 2007–2009, Texas Instruments Incorporated
Table 2-8. GMII – Lane To Functional Pin Mapping
TX_ER
TRANSMIT
CONTROL
DATA BYTE
BIT
(INPUT)
(INPUT)
TXC_[4] TXD_[7:0]
TXC_[5] TXD_[15:8]
TXC_[6] TXD_[23:16]
TXC_[7] TXD_[31:24]
TXCLK_[0]
{TX_EN,TX_ER,Data0[7:0]}
RXCLK_[0]
{RX_DV,RX_ER,Data0[7:0]}
TXCLK_[0]
{TX_EN,TX_ER,Data0[7:0]}
RXCLK_[0]
{RX_DV,RX_ER,Data0[7:0]}
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RX_DV
RX_ER
CONTROL
CONTROL BIT DATA BYTE
BIT
(OUTPUT)
(OUTPUT)
RXC_[0] RXC_[4]
RXC_[1] RXC_[5]
RXC_[2] RXC_[6]
RXC_[3] RXC_[7]
SDR Rising Edge Aligned Timing
SDR Falling Edge Aligned Timing
TLK3134
SLLS838F – MAY 2007 – REVISED DECEMBER 2009
RECEIVE TRANSMIT
CLOCK
(OUTPUT) (INPUT)
RXD_[7:0] TXCLK_[0]
RXD_[15:8] TXCLK_[1]
RXD_[23:16] TXCLK_[2]
RXD_[31:24] TXCLK_[3]
{TX_EN,TX_ER,Data1[7:0]}
{RX_DV,RX_ER,Data1[7:0]}
{TX_EN,TX_ER,Data1[7:0]}
{RX_DV,RX_ER,Data1[7:0]}
Detailed Description
TLK3134
RECEIVE
CLOCK
(OUTPUT)
RXCLK_[0]
RXCLK_[1]
RXCLK_[2]
RXCLK_[3]
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