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ADDRESS: 0x18
BIT(s)
CRPAT Error
24.15:0
counter[15:0]
(1) User has to make sure that register 23 is read first and then register 24. If user reads register 24 before reading register 23, then the
count value read through register 24 may not be correct.
ADDRESS: 0x1B
BIT(s)
27.15
Global write
27.14:12
Test Mux Select
ADDRESS: 0x1C
BIT(s)
28.15
Signal Detect
Encoder Invalid Code
28.13
Word
Decoder Invalid Code
28:12
Word
ADDRESS: 0x1D
BIT(s)
PRBS High Speed
29.15:0
Test Counter
ADDRESS: 0x1E
BIT(s)
30.15:0
Ext address control
(1) This register is not per channel basis. This register can be accessed through any of the 4 channels.
ADDRESS: 0x1F
BIT(s)
Ext address data
31.15:0
register
(1) This register is not per channel basis. This register can be accessed through any of the 4 channels.
Copyright © 2007–2009, Texas Instruments Incorporated
Table 2-87. PHY_CRPAT_PATTERN_COUNTER_2
NAME
This counter reflects LSW part of error count for CRPAT Frequency test
pattern. Counter increments for each received character that has an
error. Counter clears upon read.
Table 2-88. PHY_TEST_MODE_CONTROL
NAME
When written as 1 the settings in 27.14:12 will affect all channels of one
device simultaneously.
When written as 0 the settings in 27.14:12 are only valid for the
addressed channel.
This value always reads zero.
Mux control to select debug signals onto test mux data pins. For TI test
purposes only
Table 2-89. PHY_CHANNEL_STATUS
NAME
When high, indicates that the SERDES detected valid signal.
When high, indicates that the 1000Base-X encoder received an invalid
control word.
When high, indicates that the 1000Base-X decoder received an invalid
code word.
Table 2-90. PHY_PRBS_HIGH_SPEED_TEST_COUNTER
NAME
This counter reflects errors for PRBS (2^7) test pattern verification .
Counter increments by one for each received character that has error.
This counter saturates at 16'hffff. When read, it resets to zero and
continues to count.
Table 2-91. PHY_EXT_ADDRESS_CONTROL
NAME
This register should be written with the extended register address to be
written/read. Contents of address written in this register can be accessed
from Reg 31 (0x1F).
Table 2-92. PHY_EXT_ADDRESS_DATA
NAME
This register contains the data associated with the register address
written in Register 30 (0x1E)
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SLLS838F – MAY 2007 – REVISED DECEMBER 2009
(1)
DEFAULT: 0xFFFD
DESCRIPTION
DEFAULT: 0x7000
DESCRIPTION
DEFAULT: 0x0000
DESCRIPTION
DEFAULT: 0xFFFD
DESCRIPTION
(1)
DEFAULT: 0x0000
DESCRIPTION
(1)
DEFAULT: 0x0000
DESCRIPTION
TLK3134
TLK3134
ACCESS
COR
ACCESS
RW/SC
RW
ACCESS
RO/LL
RO/LH
ACCESS
COR
ACCESS
RW
ACCESS
RW
Detailed Description
67
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